The elite party of 90nm high-performance FPGA suppliers has just been crashed. The two big burly guards at the entrance to the VIP room were evidently not paying attention, because Lattice Semiconductor just waltzed right in – as if anybody that wanted to could whip up an FPGA family with 3.4Gbps SerDes transceivers, 2Gbps parallel I/O, up to 115K LUTs, loads of hard IP, and up to 500MHz fabric performance. Did nobody notice those 300mm wafers in their pockets?

For about a year now, only Xilinx and Altera have claimed turf in the 90nm FPGA arena. For much longer than that, Xilinx and Altera have been the only companies with devices that were serious competitors in the “high-end” FPGA race. The high-end devices really have defined the FPGA market for most of its history. Everybody not producing the densest, fastest devices was a niche player. Now, with the explosive growth in the low-cost/high-volume FPGA market (which Lattice is also crashing with their newly announced LatticeECP2 90nm family – more on that next week), high-end is only one of the major FPGA plays, but it is still vitally important.

Lattice’s new family is being announced about a year behind the more established competitors, but the time lag isn’t what one might first think. While the other suppliers announced their lines long ago, nobody is yet fully in volume production with a high-end 90nm line. Some members of competitors’ 90nm families are shipping, but there are still rumored to be yield and delivery problems on others, and still others are listed as not yet in production. Given Lattice’s track record of short announcement to delivery times, they may be ready for true volume delivery much closer to their competitors than the announcement dates would indicate.

LatticeSC is connectivity ready, with up to 32 SerDes transceivers, each capable of operatingfrom 600Mbps to 3.4Gpbs. The most recently announced competitor, Altera’s Stratix II GX, has up to 20 transceivers capable of 622 to 6.375Gbps. Xilinx has up to 24 Rocket I/O transceivers in their Virtex 4 FX capable of 622 to 10.3125Gbps. So – LatticeSC has the most transceivers, but the lowest maximum frequency. What does that mean in practical terms? It means a few of the fastest, less popular standards won’t be supported by Lattice’s family, but the majority of the mainstream gigabit serial I/O protocols, including PCI-Express, Gigabit Ethernet, XAUI, FibreChannel through 2G, SONET/SDH, and Serial RapidIO should all be within reach. Lattice claims outstanding figures for jitter, jitter tolerance, and power consumption on their transceivers, making LatticeSC an apparently strong contender for applications requiring multi-gigabit serial connectivity.

Similarly interesting is the work Lattice has invested to get up to 2Gbps speed out of their parallel I/O. For many chip-to-chip connections where backplane or off-board signal integrity is not an issue and where the design doesn’t need the additional complexity or latency of gigabit serial, fast parallel connectivity may be just what is needed. Lattice has also managed support for the highest-performance memory architectures, including DDR2, QDR2, and RLDRAM.

LatticeSC also offers what lattice calls MACO (Masked Array for Cost Optimization) blocks. Curiously, the company chose to market these blocks as “embedded structured ASIC,” although what MACO blocks actually represent is a landing space for hard-wired IP. LatticeSC devices contain up to 12 MACO blocks where high-density, high-performance IP will appear, customizing the LatticeSC devices for more specific application areas. MACO blocks will include functions like Lattices’ flexiMAC multi-protocol communications engine.

The point of MACO blocks is similar to the point of Xilinx’s various flavors of the Virtex-4 family (LX, SX, FX), or to Altera’s Stratix-II/Stratix-II GX variants. That point is this: hard IP can deliver a vast performance, power, and density advantage over the same functions implemented in FPGA fabric. However, loading every FPGA with all the hard IP anyone might want defeats the purpose by increasing the cost, complexity, and power consumption for everyone. The best strategy is to produce a variety of FPGAs with various combinations of hard IP optimized for specific application styles. In Lattice’s case, they chose the approach of leaving MACO blocks as last-minute-mask-programmable zones that will allow them to produce highly optimized programmable devices for specific application areas as they see market potential.

Lattice’s basic logic cell for LatticeSC is a variant of the venerable 4-input LUT. The family ranges from 15K to 115K LUTs (and as far as we can tell, these are “actual” LUTs with real hardware implementing each one instead of the vague “effective” logic cells quoted by other vendors.) A heads-up comparison with other vendors’ devices is difficult, because each competitor states their density in a different way. Altera is working to find a metric that will compare their 7-input variable width LUT structure with a more conventional 4-input logic cell.

On embedded block RAM, LatticeSC comes with up to 7.8 Mbits, operating at up to 500MHz. That’s more than all but Xilinx’s biggest, not-yet-shipping 4VFX140 and Altera’s EP2S180. The 500MHz data rate puts LatticeSC near the top, considering typical FPGA-industry marketing datasheet tolerances. LatticeSC’s RAM blocks can implement single-port, true dual-port, pseudo-dual-port, and FIFO. They include dedicated FIFO logic that allows FIFOs to be implemented without consuming additional LUT fabric.

For the power-conscious, LatticeSC offers a 1V power supply option. Lattice claims that this reduces core power dissipation by over 50% at a cost of only 15% in fabric performance. In many applications, the drop from 1.2V to 1V Vcc is a very simple step that could overcome a world of design difficulty. While power optimization is not a common priority among users of high-end FPGAs, heat and power supply constraints are often an issue in these systems, and cutting the FPGA power in half can have a significant impact.

On the clock management front, LatticeSC takes a “both” approach, incorporating both PLLs and DLLs. LatticeSC comes with 8 PLLs and 12 DLLs for a total of 20 clock managers per device. Using this mix-and-match approach, you can select the clocking scheme that is most efficient and appropriate for each part of your design, saving area when DLLs are appropriate, and using the additional capabilities of PLLs when they’re needed.

So, do we sense something missing here? Other high-end FPGAs typically sport another feature that’s not apparent in the LatticeSC datasheet. We looked awhile for the DSP blocks (you know the ones) with the 18X18 multipliers or multiply-accumulate with some extra control and carry logic. We finally gave up and checked with Lattice. Interestingly, we found them – in the new Lattice ECP2 low-cost series.

This represents an intriguing strategic differentiator on Lattice’s part. Lattice’s reasoning is this: high-end FPGAs (with multi-gigabit transceivers and so forth) are primarily used to solve high-speed connectivity problems in pricey, rack-mounted equipment. DSP features are more often needed in wireless, video, and imaging applications that require high-performance multipliers and the massive parallelism achievable with FPGA acceleration. These applications, however, are often in the volume range that also prefers a lower-cost device.

The upside of leaving off the DSP blocks is that if you don’t need them in your high-end FPGA, you don’t end up paying for them – in either part price or power. While detailed pricing is not yet announced, this could translate into a more favorable cost-per-feature for LatticeSC versus competing FPGAs. If you’re after the lowest price per I/O bandwidth, LatticeSC may end up looking very good.

Lattice’s recent announcements reflect an extremely ambitious undertaking on the part of the company. Their competitors pre-announced 90nm architectures, then rolled out details over a period of months, then spaced the announcement of low-cost and high-end families, then rolled out a cost-reduction strategy, all taking well over a year to get to the point where they were just beginning to ship working silicon. Lattice has launched the entire package in one great blast, catching the market (and possibly their competitors) somewhat by surprise.

In the spirit of announcing everything their competitors offer – all at once – Lattice has also pre-announced a cost-reduction service called “FreedomChip.” Lattice says details will be announced later. Our guess is that FreedomChip may be either something like A) Xilinx’s EasyPath – where FPGAs are tested with design-specific vectors and certified for use with that design only; or B) Altera’s HardCopy — where a full, mask-programmed structured ASIC is constructed to match the programmed FPGA. We’ll have to wait to see the answer.

Lattice says prototypes are available now for the LSFC25, and that “remaining devices in the family will be moved to production during 2006.” Lattice’s pricing is projected at $49 for that device in 25K quantities for 2007 shipment.

While Lattice has faced more than its share of business difficulties over the past few years, their past year of FPGA development in partnership with Fujitsu has been prolific, with numerous new product announcements (perhaps more than any other FPGA company) over the past 18 months. Their bold simultaneous entry into the 90nm fray with both high-end and low-cost families, as well as a potential cost-reduction strategy may be just the boost the company needs to become another major contender.