Geologic time is difficult for humans to visualize. Great continents slamming into each other with epic force, reshaping the earth’s surface, don’t seem so impressive when the movement is slowed down to an almost imperceptible rate. The only time we notice the effect is when transients like earthquakes, tsunamis and volcanic eruptions hint at the unwavering determination of the underlying forces. As electronic designers, however, we have some facility in dealing with alternate orders of magnitude in the time scale. We understand that nanoseconds and milliseconds are worlds apart, even though, as humans, we can’t perceive a difference in real time. We learn to look at second-order transient manifestations that occur in time we can perceive – like our FPGA going into thermal runaway or failing to configure.
At the end of 2003, we asked, “Can You Lift the Cow?” We talked about low-speed changes in a high-speed market where significant discontinuities are masked by the distorted passage of human-perceived time. This year, we look at some real-time transients that signal significant forces at work in the way we do electronic design. The big market and technology news in FPGA and structured ASIC for 2005 is plate tectonics in the design tool arena. If our semiconductor seismometers are calibrated correctly, there’s an earthquake coming soon.
On the surface, 2005 seemed like a ho-hum year in programmable logic and structured ASIC. The seasons came and went with few surprising revelations. From a silicon point of view, the major contenders had been announced or at least firmly expected by the end of 2004. FPGA market leaders Xilinx and Altera had already staked their positions in 90nm with their high-end Virtex-4 and Stratix II lines and with their low-cost, high-volume Spartan-3 and Cyclone II families. Structured ASIC players had mostly rolled out their 90nm offerings as well and were working busily to define markets for their relatively new offerings and to build sales and distribution channels that could handle the new, lower NRE business model.
The business of selling silicon is certainly more muted than the business of announcing it.
2005 was the year of transition from fantasy to fulfillment. All of the euphoric “announces world’s best” was over, and the long, arduous task of delivering production silicon with acceptable yield had begun. This week, Xilinx, the world’s largest FPGA vendor, announced shipment of their 10 millionth 90nm device. They further claimed that their contribution represents 70% of world demand. Those numbers would put worldwide 90nm FPGA consumption at a modest 14 million devices, and that number generously takes part of 2004 into account as well. With the average price of FPGAs plummeting, this still doesn’t represent a large penetration in the overall semiconductor scene. Even Xilinx’s volume pricing for their smallest Spartan-3 devices: “under $2 based on 500K unit volume, second half 2006…” speaks of a market still to come. At those order sizes, 20 orders would account for the company’s cumulative volume-to-date, and the late 2006 pricing speaks to an anticipation of better yields in the future.
What may have seemed mundane on the surface, however, was anything but. Below the boring business of 90nm market expansion, technical progress was boiling in several important areas. Non-volatile FPGAs made significant strides, as Actel, Lattice, and QuickLogic all fortified their fronts with new and diverse offerings. Actel pumped up their ProASIC3 offering with an ARM7 core and then took a radical turn toward new applications by adding analog capability to create their innovative Fusion line. Lattice Semiconductor shrugged off business difficulties to successfully launch several new low-cost FPGA families on-schedule in what should be their most successful bid yet to expand beyond their traditional CPLD market base into FPGAs. QuickLogic further refined their application-specific programmable part strategy by delivering a new line of programmable ASSPs (antifuse FPGAs in disguise) for wireless and storage applications, as well as a new line of ultra-low-power FPGAs called PolarPro.
A number of programmable platform startups made noises in the night, disturbing the general calm of “quiet mode.” Mathstar, Tabula, Ambric, Stretch, Velogix, Cradle, ElementCXI, and Achronix are rumored to be working on everything from highly optimized DSP platforms to asynchronous FPGAs running at gigahertz speeds with a variety of target markets, innovative design flows, and silicon architectures. These companies all presumably made it far enough along to convince some savvy venture capitalists that they had ideas worth exploring, and now they’re in various stages of the migration of that technology from PowerPoint to silicon. If history is any guide, only a select few will survive to get products accepted in the market, but those that do persevere have the potential to create major market and technology movement and will at least serve to keep the established players on their toes.
Structured ASIC grew stealthily over the course of 2005 with few announcements, but with ample evidence of a maturing market. ChipX, AMI, Lightspeed, LSI Logic, and NEC all offer various forms of “conventional” structured ASIC devices. They use design processes similar to traditional gate arrays to dramatically reduce NRE and mask costs for ASIC designers. On the other side of structured, eASIC and Altera have innovative offerings that somehow straddle the line between structured ASIC and FPGA. In the case of eASIC, the innovation comes in the form of what they call “standard metal,” which allows very small volume customization using e-beam personalization, reprogrammability with FPGA-like LUT structure, and higher-volume transition to mask programming. Altera’s HardCopy offers a one-to-one mask-programmed replacement for their high-end Stratix II FPGAs, allowing prototyping and early production to be completed using FPGAs followed by a seamless transition to cost-reduced structured ASIC.
Structured ASIC’s biggest challenge at this point is market awareness. Engineering teams are just not accustomed to considering structured ASIC as a system design option. Even though structured ASIC fills an enormous gap between the top of the FPGA cost/capability curve and the bottom of the cell-based ASIC viability region, most system designers haven’t yet gotten the word and don’t know what to make of the emerging technology. We’ll try to help out: “Hey, System Designers! Structured ASICs are Pretty Cool!”
In both the FPGA and structured ASIC arenas, IP came on strong with a wide range of pre-designed modules debuting for both technologies. The bulk of the IP comes from the silicon vendors themselves, but an increasing number of third parties are producing high-value IP that can be used with a variety of silicon platforms. The semiconductor vendors, realizing that they can’t be the single source for everything, have embraced third-party IP by providing well-conceived frameworks for evaluation and integration of third-party IP modules, including licensing and security support. There has also been a maturing of the IP offerings themselves, with bundles of highly targeted IP being offered for specific types of design rather than the grab-bag multiplicity of modules from the past.
Now vendors are looking smarter by focusing on high-value end applications. Instead of announcing their better mousetrap and waiting for the world to beat a path to their door, they drop in on their customer to explain how they can eradicate that specific customer’s particularly pesky mouse – the one that’s sneaking into the food cupboard at night via a tiny hole beneath the baseboard and avoiding all the normal, cheese-baited traps. This highly-focused, speak-the-customer’s-language approach represents the future of marketing as programmable logic and structured ASIC expand into various vertical markets.
Meanwhile, deep beneath the ocean floor of marketing rhetoric and inertial design philosophy, technological tectonic plates grind together with massive momentum at almost imperceptible speed. For years, there has been a precarious equilibrium of forces in EDA for FPGA. When FPGAs first arrived on the scene, FPGA vendors had to supply their own tools to customers, much like at the dawn of the ASIC industry. Commercial EDA hadn’t yet noticed the nascent FPGA market; they were far too busy making millions on tools for ASIC design. Once FPGA did show up on their radar, EDA put their toes in the water carefully. They didn’t want to distract their development teams from established, profitable product lines to dabble in an emerging market that was perceived as low-end and low return.
Because the FPGA market never developed the diversity of the ASIC market, there was no significant economy-of-scale advantage for third-party EDA companies developing vendor-independent tools. Also, since they weren’t defending the world from the evil demons of ASIC re-spin, they couldn’t command the stratospheric prices for FPGA tools that had funded their development efforts in ASIC. These two forces conspired to make FPGA a weak play for EDA. A few EDA companies stuck their toes in up to their ankles, but almost nobody was willing to risk the knees.
This understandable lack of commitment from EDA left the FPGA companies to fend for themselves in the quest for a dependable source of full-range tool solutions. They have always been able to depend on EDA for excellent point-tool support in areas like HDL simulation and synthesis, where they could leverage EDA’s ASIC-borne expertise, but they never got an above-the-knees commitment from the EDA industry to supply complete FPGA design tool flows. FPGA companies have spent years with a seesaw engagement with EDA – partnering with EDA companies to develop high-powered, jointly-marketed solutions or single-vendor OEM software to be distributed with the FPGA vendor design kits, then competing with them indirectly when they develop and deploy their own replacement solutions in those same technology areas.
While FPGA couldn’t rely on EDA and similarly didn’t want EDA companies to monopolize the design tool supply chain (as they did in ASIC), they still wanted to be able to take advantage of EDA’s technology, expertise, and development resources. For smaller FPGA companies, in-house development of a competitive, comprehensive tool suite was not an economically feasible option. For EDA, however, building a business around only second- and third-tier FPGA vendors was equally unappealing.
By these opposing forces, the balance was struck. EDA dabbled, and FPGA duplicated. EDA companies would launch a value-added capability for FPGA, and within a couple of years, the FPGA vendors would follow suit with their own in-house technology, slicing the EDA companies’ profit margins. While this may seem like a hostile market for software startups and development, a number of EDA companies, including Synplicity, Mentor, Altium, Aldec, AccelChip, Celoxica, Impulse and Magma, continue to make significant investments in FPGA tools. Synopsys, stalwart of the ASIC design tool business, has maintained an on-again – off-again relationship with FPGA, announcing, marketing, and then discontinuing a series of FPGA-related products over the past decade. Cadence has seemingly avoided the FPGA space altogether, choosing a co-existence strategy where FPGA overlaps with their board and HDL simulation offerings.
In 2005, the FPGA vendors stepped up their efforts even more. Altera and Xilinx both made major tool improvements with new versions of their design environments. They improved both in breadth and in depth, with market-widening enhancements in embedded development, DSP design, and high-level design, as well as performance improvements in standard areas like synthesis and place-and-route. Both Altera and Xilinx now offer physical synthesis with their design flows – a major improvement from the past. Interestingly, both companies have embarked on power estimation and optimization efforts in advance of the EDA companies, breaking the usual “EDA first” rule.
EDA responded with a volley of enhancements of their own, headlined by Synplicity’s announcement of their completely overhauled synthesis and physical synthesis flagship now dubbed “Premier”. Premier takes physical synthesis for FPGAs to its next logical phase – combining physical and logical optimization into one step. While such techniques have been prevalent in ASIC design for several years, this is their first appearance in FPGA. At the same time, Synplicity has established another trend by practically cornering the market for structured ASIC implementation tools. If Synplicity’s bet is right, they could leapfrog some of the traditional EDA giants by picking all the right horses in the new ASIC race.
This year, however, the percentage of FPGA designs done using only FPGA vendor-supplied tools apparently increased significantly. This could be the earthquake that signals the decisive shift in design tool sourcing for FPGA. If FPGA vendors now offer tools that are “good enough” for most applications, the commercial EDA for FPGA market could either collapse or change dramatically. Without the support of the common designer, will commercial tool suppliers have enough economic justification to develop new technologies?
It will take some time and a few more samples to see what these signals really mean. We plan to revisit this issue in depth in a future article. Right now, though, don’t be fooled by the outer calm of the market. As we enter 2006, chaos rages just beneath that outer layer. When something shakes lose at the surface, we here at FPGA and Structured ASIC Journal will be ready to give you our take on it. Thanks for another great year!
