Sometimes, even the experts get fooled. Anybody who is intimately familiar with the FPGA industry would probably have predicted the same thing. With the epic Godzilla versus Mothra game of marketing and product one-upsmanship raging between rivals Xilinx and Altera for the past decade, the next move is often simple to anticipate. In the most recent rounds of action: Xilinx packs a hard punch introducing low-cost Spartan-3 as the first 90nm FPGA. Altera strikes back with Stratix-II as the first 90nm high-speed, high-density flagship offering. Each side then counters with the piece they’re missing, Altera with Cyclone II 90nm low-cost line, and Xilinx with Virtex 4, their 90nm flagship family. Now both sides assess their positions and prepare the next assault…

Since Xilinx’s V4 line also included high-speed SerDes (up to 10Gbps) Altera’s next play was obvious. Like chess masters zipping through a well-known opening, the moves are practically choreographed in advance. Altera just needed to roll out the “GX” extension to Stratix II indicating that they too had a 90nm SerDes capability. Given the industry’s propensity for superlatives, of course, Altera would probably be announcing something like rare-air 12Gbps SerDes so they could be “20% faster”… for a month or two at least, until…

Remarkably, Altera did the smart thing instead.

Not everybody needs a Formula-1 Ferrari to schlep their suits to the cleaners. In fact, the special design features that allow the car to travel at over 200MPH and handle over 1G lateral acceleration could actually make it a less-than-ideal vehicle for transporting laundry on city streets. There’s no good place to hang clothes, and the plastic bags would probably catch fire on the exhaust plenum. The same sort of thing is true for SerDes I/O. The design tradeoffs that allow transceivers to operate at 10Gbps can lead to sub-optimal signal integrity and higher power consumption at lower speeds.

Altera looked at today’s SerDes applications, picked the speed range most commonly used by their target markets, crazy-glued their egos to the desk, and designed the most efficient transceivers they could manage for the 622Mbps to 6.375Gbps range.

SerDes (Serialize/De-serialize) is a generic term that describes the function of transceivers that provide high-speed serial I/O functionality for a wide variety of standards and protocols. SerDes I/O has been rapidly displacing wide parallel busses in communications backplane applications, and is now moving into a wide variety of other applications where large amounts of data must be moved between physically separated devices. When adding SerDes capability to an FPGA, the FPGA vendor has to design special transceivers to support a diverse set of design goals over a huge speed range. This is a challenging engineering task involving numerous tradeoffs and compromises as well as a heavy dose of the dreaded analog domain. The proof in the pudding is the hole in your eye-diagram, and getting a big one over a wide range of conditions is difficult indeed.

For Stratix II GX, Altera chose to modify its highly successful Stratix II architecture, replacing one side of the I/O ring with up to 20 transceivers (depending on device size). Obviously, Altera has focused their energy on making these transceivers operate with the best possible signal integrity, and at the lowest possible power. They’ve pulled several tricks out of their hat in order to get there, including multiple PLLs optimized for different frequency ranges, pre-emphasis, equalization, and signal-integrity optimized packages with more I/O pins for better power/ground distribution.

Altera has also created a Matlab-based tool for parameterized simulation of backplane characteristics, allowing the pre-emphasis to be optimized without complex spice models. The Matlab tool makes short work of an arduous task, as setting up accurate models of a high-speed serial design is tedious, tricky business. Altera claims the tool turns a three-week process into a 45-minute task, and we wouldn’t be too surprised if they were right.

This Matlab integration hints at another priority Altera maintained in the development of S2GX – ease of use. In the past, most users of SerDes I/O were battle-hardened veterans with copious amounts of experience maintaining signal integrity across high-performance backplanes. Today, however, with the proliferation of protocols like PCI Express, the masses (those of us with less signal integrity savvy) are starting to storm the SerDes castle. If we’re going to be able to get good results without bringing in full-time Altera applications engineers to watch our backs, the design of the device and its supporting ecosystem needs to be novice-friendly.

In the spirit of ease-of-use, Altera is providing a robust support environment including software, IP, system models, and reference designs. They’ve also built as much of the supporting hardware as possible into the transceivers themselves, eliminating the need to add additional external device support. They are offering protocol-specific development boards for PCI-Express and SDI – two of the most common standards where there is likely to be widespread new user adoption. Altera has clearly done their marketing homework before launching this new family, and the product planning discipline should pay off.

Before we all start to mourn the end of the epic battle for specification supremacy, however, let’s direct our attention to the power portion of the datasheet. Here, at last, superlatives are flying at full-tilt boogie. Altera is billing Stratix II GX as “The Lowest Power FPGA with Embedded Transceivers” and following with claims of power dissipation pegged at less than 50% of competitive products. While it pays to be skeptical of any vendor’s power claims (your mileage may vary – a lot!) it does look like Altera has cooled off the transceiver technology significantly compared with previous offerings.

For now, Stratix II GX should heat up the high-end FPGA race even more, and designers will benefit with more and more varied options for a variety of emerging serial standards. Increased competition almost always benefits the customer, so we should expect to see results when we roll SerDes into our designs.

As far as the Altera-Xilinx battle goes, what will the next chapter in the dynamic duo’s duel bring us? We’re going to play our predictions close to the vest for the time being, but after Altera’s announcement of this family, we wouldn’t be too surprised to be surprised again.