A little over a year ago, when we wrote our last feature on high-speed serial I/O, you might have felt safe. You could read the article with a secure fascination, isolated from personal involvement with the risks of the technology and amused at the lengths to which those telecom types would go in order to cram more bandwidth onto the backplane – safe in the knowledge that your own precisely-tuned parallel busses were merrily megabitting away on your little low-tech circuit boards. Now, the subject may feel a bit more uncomfortable. With standards like PCI Express gaining increasing momentum, your inevitable day of doom looms large. It won’t be long before you’ll have to walk over to your technical bookshelf (the dusty end) and pick up that college analog textbook that you’ve schlepped along with you through your last four jobs without cracking the cover. It’s the one that you didn’t return to the bookstore for credit because you hoped that its presence in your bookcase would camouflage the fact that your digitally-biased brain remembered absolutely nothing from any of those classes.
Try to remain calm. The industry feels your fear.
“Designer education is the biggest barrier to SerDes adoption today,” says Abhijit Athavale, Serial Connectivity Marketing Manager at Xilinx. “At first, it was just the top-tier telecom customers that were interested in SerDes. They were comfortable with the analog design component, the signal integrity issues, and the idea of bit-error-rates. Mainstream designers are more suspicious of any situation where errors are assumed.”
These mainstream designers are adopting SerDes in droves, however, and the transition is a tricky one. Vendors are responding with cookbook-style recipes for SerDes success. “Agilent and Tektronix won’t be selling many $100K scopes to Mom and Pop shops designing with PCI Express,” Athavale continues. “We’re working hard to provide detailed guidelines that will help people succeed. Today, if someone wants to do a PCI design, they can buy the spec, follow the guidelines to a T, and have it work, even if they don’t simulate. We need that kind of comfort level for SerDes.”
Mom and Pop aren’t jumping into the deep end of the SerDes pool at 10Gbps just yet, though [see sidebar article]. “More than 50% of transceiver applications are still below 2.5 Gbps,” says David Greenfield, Senior Director of Product Marketing at Altera, “though customers are indeed increasing both speeds and channel count. Many customers are pushing speeds on existing backplanes (backplanes initially designed to support 1.0 – 2.5 Gbps) up to 3.125 Gbps. Customers are also pushing to next generation standards (i.e. FibreChannel running at faster speeds). At the same time, many customers are still in the process of making the transition from parallel to serial interfaces.”
FPGAs have a long history with SerDes. In fact, SerDes has become one of the compelling arguments in favor of leveraging FPGA technology. Vadim Shain, System Application Engineering Manager for leading ASIC vendor NEC explains: “Moving to integrated SerDes in an ASIC is usually a second-pass cost-reduction step. People initially implement their first pass with discrete SerDes, or SerDes on an FPGA. Once they’re confident with their design, they take the next step and move to an ASIC with integrated SerDes technology.”
The flexibility of FPGAs in the face of changing standards was a compelling reason that the backplane bunch adopted them in the first place. With the crunch of increasing bandwidth requirements fighting against dwindling parallel backplane resources, a plethora of protocols and standards for high-speed serial design exploded onto the scene. Not wanting to design themselves into a corner, engineers turned to FPGAs to future-proof their SerDes-based systems. If they picked the wrong standard, or if their chosen standard changed underneath them, they could count on in-system reprogrammability to bail them out.
Now, with FPGAs becoming the star of many designs where they previously were only supporting actors, the trend is moving toward integrating SerDes into multi-function, system-level platform FPGAs. At least one vendor sees that migration as a false economy, however. “It’s fundamentally difficult to mix analog and digital,” says Ian Land – Senior Manager of IP Solutions Product Marketing at Actel. “When you try this with a complex device like a sophisticated FPGA, the noise of the digital part can be overpowering, and it limits what you can do with the high-speed serial interface. It also requires different power supplies and more elaborate support. The total chip count and board area for using integrated SerDes on an FPGA can actually exceed what you’d have using an Actel ProASIC device in combination with discrete SerDes. There’s also some question on the cost justification of integrating. You can add discrete SerDes for something like $10, but the cost of moving to an FPGA with integrated SerDes could be much higher.”
If your system is already working with FPGA or discrete SerDes, and you want to cost-reduce for big volumes, the ASIC and structured-ASIC suppliers are waiting with open arms. Both NEC and LSI logic have made significant investments in high-speed serial I/O, offering that technology in both their structured ASIC lines and their full-blown cell-based ASICs. “LSI shipped its first integrated gigabit SerDes in April 1996,” says Harmel Sangha, director of coreware IP marketing for LSI Logic. Our investment actually started back in 1994, so we have a very long history with this technology. LSI saw the potential of this concept early on and wanted to capitalize and provide silicon solutions. Today, we are shipping ASIC products with 64Gb SerDes on a die.”
Both LSI and NEC developed their high-speed serial technology for their cell-based lines, and then migrated that technology into their newer structured ASIC offerings. “Our new ISSP90 family uses exactly the same macro as our cell-based ASICs,” continues NECs Shain. “We invested heavily in developing our technology, including participating in the many standards bodies. While the standards work is a lot of investment, it is crucial to our success. Some companies try to go it alone and find that they have compatibility problems when their devices try to communicate with others.”
The experts agree that the biggest challenges of high-speed serial design are the verification and testability of the completed system and dealing with the signal integrity issues from routing high frequency differential pairs through the circuit board. Toward that end, tool providers are developing and adapting their solutions to address the particular needs of designers coping with SerDes requirements. “We have continued to make progress in SerDes support with both our HyperLynx and ICX solutions,” says Kevin Cohan, Mentor’s Marketing Manager for High-Speed pc-Board Signal-Integrity products. “The FPGA vendors are bringing down the barriers to adoption by hiding a lot of the complexity. Initially, they were only supplying HSPICE models, and many digital design teams were not equipped or trained to do the required level of HSPICE simulation. Now, we’re working with FPGA vendors to provide models that tools like HyperLynx and ICX can handle, simplifying things significantly for the designer.”
In addition to advanced model support, EDA vendors are adding more SerDes-specific features in their tools like multi-bit stimulus over long simulation runs that can be presented in the form of an eye diagram. As the tools and technology become more commoditized, the biggest remaining barriers are designer awareness and education. “Overcoming fear and uncertainty are the biggest obstacles,” Mentor’s Cohan continues. “Now that we see knowledge of the technology spreading and increasing, designers are becoming aware that the technology is not so daunting. When we first offered full-day workshops on the topic, the designers that came in seemed a little shell-shocked. Since then, we’ve been refining and tailoring the materials more to the audience. There’s noticeable progress in people getting over their fear and picking up the tools and models.”
Before you jump into the SerDes sea without a life raft, however, be aware that it may be a long swim to shore. “If you make the technology seem like it’s so easy, it can be misleading,” continues Cohan. “In the end, you still have to tune and figure pre-emphasis, decide if your interconnect models are sufficient, and get the whole thing working.” NEC’s Shain agrees: “When I walk through a trade show and see a board running with a perfect eye-diagram on a scope, I always ask ‘How long did this project take from beginning to end?’ Usually the answer comes back ‘years’.”
Who’s taking up the challenge most and sliding SerDes into their designs? “We’re seeing a lot of industries like medical driving new requirements for SerDes,” Shain continues. “Their requirements aren’t as tricky as in telecom/datacom, but their instruments are getting more sophisticated and demanding the additional bandwidth.” “We also see adoption even in Mil/Aero where you might expect it to be slower,” says Mentor’s Cohan. “When these designers found they could reduce a wide bus to a couple of tracks and increase bandwidth at the same time, their management came back and said ‘Great, now we can use all those extra tracks for more channels.’ Now they’ve got as many tracks as before, but all of them are running at gigabit speeds.”
When your team takes the plunge, be sure you’re well educated and equipped. It’s probably a good idea to start with the technology you choose and move outward from there. If you plan to use integrated SerDes on an FPGA, for example, follow that vendor’s recommendations religiously. It’ll increase your chances of first-pass success, and it will also make your design much easier to support if you run into difficulties. This is not a good place to add in your own clever engineering shortcut in hopes of shaving off a little design time or cost. If you’re still scared, pull that analog textbook out just a little on the shelf where it can be noticed. There’s a good chance that somebody else on your team will come by and “borrow” it, and you may be able to postpone the entire ordeal.
