A decade ago, memory was not mentioned in the same breath as programmable logic. Each component type had its own role in system design, and different design team members were typically involved with their selection and use. Once FPGAs became serious system components, they began to be paired with memory in switching and network applications. During that period, however, the cost of the FPGAs (sometimes thousands of dollars per device) usually dwarfed the RAM budget. Memory was selected for its speed, and interfacing was a simple matter of putting out an address and latching in some data.

Today, however, the advent of embedded processing applications on FPGAs and a dramatic reduction in device costs have conspired to complicate the memory picture considerably. With high-volume, low-cost applications being developed around FPGA platforms, the appetite for RAM is increasing, and the price of memory is a significant portion of many designs’ total system cost. While FPGA vendors have increased the amount and variety of on-chip memory available, most applications using an embedded processor on an FPGA will still require external memory.

System designers face a challenge in selecting the RAM that will meet system performance goals, is cost effective, and will be available in easy supply for the duration of their product life cycle. On top of that, the memory that meets those requirements is most often a high-performance DRAM with complex and challenging interface constraints. For most applications, it pays to stay with readily available, proven memory solutions.

If you want to optimize price-per-bit, the best strategy is to follow the PC market. “With today’s long product life cycles, it is important to choose a RAM technology that has legs,” says Jim Elliott, Associate Director of DRAM products at Samsung. “You need a product that will be available at a competitive price for the duration of your production cycle. In today’s market, the sweet spot is components with a 256Mbit density.” Price-wise, moving either direction from the sweet spot will result in higher cost-per-bit. A 64Mbit device might be more than ¼ the price of 256, and a 512Mbit device might be more than double. “The farther you go off the beaten path,” Elliott continues, “the price goes up and the supply and availability go down. The point moves every one and a half to two years, so you should consider your launch date and choose a density accordingly.”

(Diagram courtesy of Samsung Electronics.)

As DRAM has tracked Moore’s law, speed and density are up, price and power are down, and interface complexity is on the increase. The most common DRAM technology today is double data rate (DDR) SDRAM. As the technology moves from DDR to DDR2, there will be an increase in data rate and a decrease in supply voltage. While the speed increase and power reduction are nice, the higher frequency of operation requires much greater care in the design of the FPGA I/O and in the layout of the printed circuit board (PCB). Still on the drawing board is a SERDES-based interface standard (DDR3) which may reduce the complexity of board and interface design, but DDR3 implementation and availability is still a few years away.

For now, if you’re using commodity DRAM devices, you’ll want to use an out-of-the-box memory controller. Re-inventing the wheel on memory access is not only a good way to turn an otherwise exciting project into an exercise in frustration, it can result in disaster when trying to achieve timing closure in your system. Pre-designed controllers from 3 rd party vendors or from your FPGA supplier are well worth the cost, since they save so much in project risk, schedule, and headache.

Denali has built a major business around memory controller IP and the associated verification components. Denali’s Databahn generates memory controllers for high-speed DRAM, and their MMAV verification IP handles the complex task of verifying the interface in your design. “With FPGA designs reaching the complexity previously found only in ASIC, the need for sophisticated verification is increasing,” says Kevin Silver, Vice President of Marketing at Denali. “We put an emphasis on verification in our IP with two to four times more checking and capabilities like back-door loading that simplify the verification process.”

With more and more ASIC designs being verified in FPGA and increasing numbers of FPGA designs being cost-reduced in ASIC or structured-ASIC technologies, it pays to develop a strategy for memory interface design and verification up front. Verification of memory interfaces is subtler than most logic, requiring an emphasis on error detection and handling as well as careful timing analysis of the full board-based system.

Recognizing that external memory is playing an increasingly important role in FPGA-based development, the FPGA vendors themselves are investing heavily in tools and IP to support memory interface development. “Altera provides a complete suite of cores, boards, analysis tools, and guidelines for memory design,” says Eugene Ahn, Product Marketing Manager for Altera’s IP business unit. “We work with memory vendors on interoperability and development and verification solutions to verify that popular memories are supported. We made a significant investment in the I/O circuitry in our Stratix, Stratix II, and Cyclone lines to support and simplify memory interface design. Stratix’s dedicated data strobe phase shift circuitry, for example, makes memory timing design much easier.”

Xilinx’s Advanced Memory Development System provides a dedicated hardware platform with software support for developing and testing a variety of interfaces with their Virtex 4 FPGAs including DDR, DDR2, FCRAM II, RLDRAM II, and QDR II SRAM. While commodity DRAM may be adequate for many applications, some applications require the high-speed, lower latency technologies such as reduced latency DRAM (RLDRAM). The diversity of RAM requirements, the complexity of many of today’s standards, and the rapid evolution of memory technologies have pushed FPGA vendors to invest heavily in memory support. Actel, Altera, Lattice, QuickLogic, and Xilinx all offer at least memory controllers supporting current DRAM standards. Many go much farther with specialized I/O modes, IP cores, development tools, verification solutions, design guidelines, and reference designs to keep up with increasing customer demands.

This sudden wave of sophisticated memory support is yet another “coming of age” sign for the FPGA industry. As FPGAs work their way up from supporting roles into star players in many systems, their entourage of accompanying and supporting technologies keeps growing. Each new area, whether memory interface, embedded software support, digital signal processing performance, SERDES I/O, or some new specialty, provides an opportunity for new niche players to join the programmable logic party, as well as giving the established cast of characters another opportunity to differentiate themselves from the competition.