Light the candles …er… candle, sing the song, pummel the piñata, and uncork the champagne. It’s been one year since FPGA Journal’s first edition, and it’s time to look back and celebrate our inaugural year. Our lights first came on October 1, 2003 when FPGA Journal Update Volume I Number 1 went out to about 1,000 early subscribers. During the year that followed, our newsletter subscription base has grown to over 8,500 and our web audience to over 34,000 readers in 87 countries.
We’ve worked hard over the past year to keep you informed, entertained and even a little intrigued as we’ve covered the events and evolution of programmable logic technology, tools, techniques and trends. This week, we thought we’d review a few of the more interesting things we’ve bumped into over the past twelve months and kick off year number two with a bang.
According to the information that you, our readers, have supplied, most of you are design engineers, engineering management, or executives overseeing engineering development projects. Some of you have been designing with programmable logic for years, and others are just starting out in programmable logic from backgrounds as diverse as embedded systems programming, digital signal processing, ASIC design, and system-on-board design. While the majority of you are working electrical, software, and systems engineering professionals, over 20% are either educators or students, and just over 10% are “industry insiders” working for programmable logic or EDA companies or distributors. About half of you (just over 18,000) visit our site at least once a month, and many visit almost every day.
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“FPGA and Programmable Logic Journal fills a void in the FPGA community with its in-depth, articulate and witty approach to analysis of important industry issues. With its fresh take on programmable logic, it has become a key source of information and commentary on the topics that matter most to anyone involved in the FPGA industry.” -John East, CEO, Actel |
During our first year, we published 91 original feature articles as well as several hundred news stories. Our most popular article of the year was our June 1, 2004 summary of FPGA simulation techniques titled “FPGA Simulation – Forget what you learned in ASIC design.” In it, we challenged the notion of “FPGA verification” and discussed how most HDL simulation is used for debugging rather than verification purposes.
We get a lot of interesting and informative feedback from readers. In the FPGA simulation article, we claimed that “ “Features like assertions (which are finding increasing use in ASIC verification) have little utility in the typical FPGA design flow.” A reader with considerable experience in both FPGA and ASIC design disagreed:
“This statement is patently wrong. Assertions have utility anywhere you care to use them. A sound engineering approach is to put gate-keeper monitors on all inter-module interfaces to immediately isolate bugs to the module. You don’t need a fancy assertion language like PSL/sugar to implement these but it makes it easier.
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“In a short period of time, FPGA and Programmable Logic Journal has become a key place to go on the web for comprehensive coverage of programmable logic technology. Kevin’s well written articles and contributed pieces from industry leaders make FPGA and Programmable Logic Journal a ‘must read’ for anyone who is using, or thinking of using, programmable logic.” – Tim Southgate, Vice President of Software |
I firmly believe that the more upfront work you do (writing specs, developing re-useable IP & model libraries, testing your design before the PCB comes back, etc.) pays dividends. If you think you can just test some modules, fire up an FPGA and start probing you’re nuts. Your approach may get the first design out quicker but mine most definitely will get the next 10 out quicker.”
Some of our articles generate a lot of feedback. Usually, it’s because we hit on a topic area where there is significant passion and some disagreement in the field. When we published our “Terminology Tango 101” article discussing (somewhat tongue-in-cheek) the obfuscation of FPGA specifications through creative metrics, we were swamped with reader comments:
“I just wanted to let you know that I thought this was a great article describing one of the most confusing subjects of fpga/cpld/asic design: the ‘number of (equivalent) gates’.
It’s refreshing to see that I am not alone in trying to sort thru the marketing mumble of convoluted terms.
Thanks for your refreshing insight into a marketing pariah.”
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We’d also like to thank a few people who had a tremendous impact on FPGA Journal’s success during this first year: Kayla Kurucz for her tireless efforts in business development Laura Domela for her superb layout, web design, and graphic design Shirley Rice for her outstanding copy editing Stephen Howard-Sarin for his generous expert advice |
Some offered additional suggestions:
“I just wanted to say that I enjoyed your Terminology Tango 101 article immensely! Choosing the right chip is always tricky for FPGA designers, but each works out some rules of thumb for himself or herself over the years…
My own formula for how many FPGAs are needed on an FPGA prototyping board is as follows: Use a 5:1 ratio of system gates to ASIC gates and expect only 50% utilization in the FPGA (for performance and quick fit). So, a 5 million gate ASIC design needs 50 million system gates, or seven [Xilinx] XC2V8000’s. An unwary soul might have thought his or her 5 million gates would have fit into just the one ‘8 million gate’ XC2V8000 with room to spare. D’Oh!
To be fair, most FPGA Vendor FAE’s would provide sound guidance in such situations, but the user has to know to ask the question.”
In the same vein:
“It is actually quite simple… as you pointed out, the 250k quantity 18 months from now pricing does not apply to most of us. Also gate count at the beginning of a project is an (almost) unknown and therefore a useless measure anyway. Clock speed is simple, too: take max published speed, divide by 4, and if it is still above your target speed, the fpga is good. So, here is the formula:
Device in stock at distributor (most important feature, if it is not satisfied all others are useless) that features enough ram (or other specialty features) and has enough pins and is as big as possible without breaking your budget = Ideal FPGA.”
“Great article. I’ve been there and done that and ran into all the problems you brought up.”
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We’d like to thank the sponsors who have made it possible for us to continue FPGA Journal through this most challenging phase for any new endeavor. Their confidence in us has kept the lights on and the bills paid so we can continue bringing you this publication. They are: Semiconductor Vendors: EDA Vendors:
Distributors: |
We also began our series of executive focus articles where we sit down with the most innovative and influential people in the programmable logic business to talk about their views on current trends and technology. We brought you articles featuring:
- John East of Actel
- John Daane of Altera
- Ken McElvain of Synplicity
- Cyrus Tsui of Lattice Semiconductor
- Jason Cong of UCLA and Magma Design Automation
We appreciate the time these experts shared with us to bring you their insight on the direction of our industry. We plan to continue this series into year two and already have a number of exciting executive features lined up.
Few topics in the past year have generated as much interest as digital signal processing (DSP) applications of FPGAs. The performance potential afforded by the combination of embedded processors and hardware acceleration of compute-intensive functions such as multiplication is too much for many designers to resist. We’ve been there with you, publishing a wealth of original articles on the topic, such as:
:: Beyond Processors – Implementing high-performance DSP algorithms in FPGA (read)
:: Evaluating Performance – FPGAs vs. DSPs by Jeff Bier of BDTI (read)
:: What’s the Right Language for DSP System-Level Design? by Tom Feist of AccelChip (read)
:: Using FPGAs for DSP Image Processing by R. Williams of Hunt Engineering (read)
:: DSP on FPGA Reduces System Cost by Peter Baran of BeHere Technologies (read)
:: Top-Down DSP Design Flow to Silicon Implementation by Dan Ganousis of AccelChip (read)
:: DSP Heats Up – Synplicity Enters DSP Synthesis (read)
:: Algorithms to Silicon by Tom Feist of AccelChip (read)
:: High-Performance DSP Capability Within an Optimized Low-Cost FPGA Architecture by Gordon Hands of Lattice Semiconductor (read)
We also had tremendous readership for our series of articles on handling the difficulties of integrating modern FPGAs into board-based systems, a number of pieces on the explosive embedded systems-on-FPGA field, and the many features we’ve done on design tools and the companies that supply them. Certainly the most controversial tool-related article of the year was “DAC’s Dangerous Undertones,” where we examined the dilemma faced by major EDA companies as the market shifts from a low volume, high price model to a high volume, low price model. Many readers felt we’d hit on a pocket of profundity while others believed we were prematurely announcing the demise of a vivacious industry.
During the year, we saw exciting and interesting product releases like Altera’s Max II (an FPGA pretending to be a CPLD), Altium’s Nexar (design tools for FPGAs pretending to be PCBs), Xilinx’s Virtex 4 (an FPGA pretending to be a structured ASIC), and too many more to list here. We tried to bring you the most accurate and complete technical information available while indulging in the occasional playful prod at the vendors and at ourselves.
In retrospect, it was a fabulous first year for us, and we’re extremely excited about what we have planned for year number two. Please keep those comments coming. It helps us keep focused on what you want to see from the industry’s premiere programmable logic publication.
