In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we could successfully design correctly using current methodologies. Speculation ran rampant that large amounts of RAM, immense IP blocks, and system-on-chip integration would help us fill some of the space, but the overall question remained.

When FPGAs burst onto the scene, few noticed that they were quietly answering the “white space” question. By introducing a 5-10X area penalty for the privilege of programmability, FPGAs brought the whole problem down to earth again by providing us with a much safer, more practical, and more versatile implementation fabric that was unfortunately also about a decade back on the Moore’s Law trail. Suddenly, with programmable logic design, our old friends power, performance, and price were problems again and we no longer had to worry about “white space.” Instead, we had a new problem: “the gap.”

“The gap” is the area in-between FPGA and ASIC. On the FPGA side of “the gap” we have time-to-market, zero NRE cost, flexibility, upgradeability, low risk, cheap design tools, and a host of other benefits. On the ASIC side we have power, performance, unit price and functionality that cannot yet be duplicated on FPGA. In between, where the sweet spot probably lies for many, many applications, is “the gap”.

Today, on each side of “the gap” there is a race toward center. Semiconductor vendors on both sides are pushing toward that sweet spot, trying to win over the lucrative middle-ground market. With high-end cell-based ASIC only being for the strong of heart and pocketbook, and FPGAs only for those with low production volumes and high power budgets, an alternative is needed that offers less risk, faster time-to-market and lower development cost than ASIC; with more performance, lower unit cost, and higher density than FPGAs.

From the ASIC side, vendors have created “structured ASIC” technology (please, please don’t point out that these are gate arrays. Everyone knows that gate arrays have long since fallen out of favor). Structured ASIC devices look a lot like mask-programmed FPGAs. Unlike cell-based ASICs, they are fixed architectures and only a small number of layers of customization determine the final personalization. Compared with cell-based ASIC, structured ASICs are lower NRE, faster to market, and easier and lower risk to design.

On the FPGA side of “the gap” there are a number of new technologies. This week, Xilinx released details of their upcoming Virtex 4 family which clearly is designed to take a major step into “the gap”. Unlike rival Altera’s “HardCopy” (a structured-ASIC like approach that offers smooth transition from prototyping/early-production in FPGA to cost reduction and performance improvement in a mask-programmed version of the same basic architecture,) Xilinx’s Virtex 4 family, based on their previously announced ASMBL architecture, is still fully programmable and an FPGA at heart.

As FPGAs have grown larger, faster, and more capable, vendors added more and more “standard” features to make them appealing for various applications. Hard-wired multipliers, block RAM, embedded processors, and gigabit I/O all add much needed capability for some, but raise the cost of the device unnecessarily for others. As vendors added greater varieties and quantities of embedded features, they moved toward devices that were usable for all, but optimal for none. Virtex-4 breaks that mold.

The idea of Virtex-4’s ASMBL architecture is to add another dimension to the device selection matrix. In the past, designers could choose larger or smaller parts, and faster or slower parts within the same family. The largest parts had the biggest helpings of advanced features, and the smaller parts had reduced portions of the same. With Virtex 4, there is another axis added to the equation. Designers can now choose parts with varying mixes of special features more appropriate to their application. The initial Virtex-4 family includes three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high performance signal processing, and Virtex-4 FX for embedded processing and high-speed serial connectivity. Each version has a different mix of the special features and comes in a range of density to cover a variety of application sizes.

Tuning the feature mix propels Xilinx farther into the lucrative edge of “the gap.” While Virtex-4 is still an FPGA, the ability to choose a feature mix suited to your application allows you to go to production with a cheaper part while still retaining reprogrammability. Xilinx’s first announcement of the ASMBL architecture generated some confusion, but the Virtex-4 details aim to clear that up. Even the meaning of the ASMBL acronym has been fine-tuned from “Application Specific…” to“Advanced Silicon Modular Block” to clarify the fact that the family represents a small number of domain optimized variants rather than a large number of application-specific ones.

The selection of the particular variants required a lot of careful marketing research on Xilinx’s part. Designs from every application domain were analyzed, and customers from a wide variety of industries were interviewed in calculating the required mix of features such as processors, RAM, DSP blocks, and I/Os. While many applications could be implemented on any of the variants, one version will usually offer a mix that is more advantageous in terms of overall system cost.

Virtex-4 was designed from the ground-up to take advantage of the current state-of-the-art cost reduction technologies including 90nm geometry, 300mm wafers, and flip-chip packaging. Flip-chip, in particular, enables Virtex-4’s column-based feature architecture and eliminates the requirement that a device be either core or I/O limited due to perimeter-based I/O limitations. It also allows better power and clock distribution which are key to success given the constraints posed by 90nm.

With the column-based architecture and no I/O ring, the rules and constraints for placement change somewhat. Given the size and complexity of the designs likely destined for Virtex-4, this could pose some challenges for timing closure on high-performance design. Xilinx gave some hint as to their strategy for addressing the placement and incrementality issues with this week’s announcement of their acquisition of Hier Design, Inc. Hier Design’s PlanAhead software is an ASIC-strength hierarchical floorplanner already used by a number of Xilinx customers. While PlanAhead is an asset in current Xilinx FPGA families, it will likely be a huge advantage given the architecture and density of Virtex-4.

Cost-reduction is clearly the priority as Virtex-4 was obviously created as not just another prototyping platform. To further reduce device costs in production, Xilinx is once again touting its “EasyPath” program where devices are tested with application-specific vectors and only required to pass for the resources used by that design. This allows lower production costs for designs that do not require reprogrammability.

There are both soft- and hard-core processor options available with Virtex-4. The MicroBlaze soft processor can be used with any of the variants, and the PowerPC hard-core processor is included on the FX version. The use of embedded processors makes Virtex-4 not only a capable reconfigurable computing platform, but moves the design process more toward iterative, hardware-in-the-loop design and partitioning of hardware and software. Soon, the combined leverages of reduced risk, dramatically shorter design cycles, and zero NRE will move all but the highest-volume, highest-performance applications away from cell-based ASIC implementation toward more flexible, forgiving architectures like Virtex-4.

The tools for Virtex-4 are already being used by early customers trying out their favorite designs and proving the flow. Xilinx says engineering samples of the LX versions will be available in summer 2004, with SX and FX to follow. No volume shipment date has yet been given.

Virtex-4 is an ambitious undertaking, even for the industry leader as it involves new and untested innovation in architecture, tools, process and packaging. As additional details are released, it will be interesting to see how Virtex-4 stacks up against other options for getting sophisticated, complex, high-performance designs into production not just quickly and with low risk, but with lower production cost than traditional high-end FPGAs would allow.