industry news
Subscribe Now

Cadence to Expand Verification Solution with Acquisition of Jasper Design Automation

  • Increasing verification complexity is driving the need for multiple complementary verification approaches including formal analysis
  • Jasper is a leader in the fast-growing formal analysis sector and targets a broad range of complex verification challenges
  • The combination will expand differentiation of the industry’s strongest and broadest system verification offering

San Jose, CA., April 21, 2014 – Cadence Design Systems, Inc. (NASDAQ:CDNS), a leader in global electronic design innovation, today announced that it has entered into a definitive agreement to acquire Jasper Design Automation, Inc., a leading provider of formal analysis solutions, for approximately $170 million in cash. Jasper had approximately $24 million of cash, cash equivalents and short-term investments as of December 31, 2013.

Jasper Design Automation is a market and technology leader in the fast-growing formal analysis sector, providing multiple verification solutions (Verification Apps) built on the JasperGold® platform. Jasper’s customers include many of the top systems, semiconductor and IP companies. These companies, which are also Cadence customers, are increasingly adopting formal analysis to complement traditional verification methods, so as to better address the challenge of verifying increasingly complex and flexible IP designs and systems-on-chip (SoCs). With verification representing over 70% of the cost of developing a system-on-chip, it has become the top system and SoC development challenge and is the critical factor for time-to-market.

Jasper’s technology strengths are highly complementary to Cadence’s System Development Suite, which has been the standard bearer for integrated system verification solutions since 2011. The combination will expand differentiation of the industry’s strongest and broadest system verification platform, and will be tightly integrated with Cadence’s common debug analysis, formal and semi-formal solutions, simulation, acceleration, emulation and prototyping platforms, while leveraging its unified verification planning and metric-driven verification flow. In addition, the combination of extensive dynamic and formal VIP portfolios will be particularly well suited to enable embedded processor system verification.

“Jasper’s products are recognized as the technology leaders in formal analysis, targeting complex verification challenges and increasing overall verification productivity,” said Charlie Huang, senior vice president of the System & Verification Group and Worldwide Field Operations at Cadence.  “Jasper’s formal analysis solutions are used by customers today alongside Cadence’s metric-driven verification flow to form a broad verification solution. We look forward to welcoming Jasper’s strong formal development expertise and skilled team to Cadence.”

The combination of Jasper and Incisive® Formal technologies and expertise will result in the most complete formal and semi-formal offerings in the industry. With its broader verification portfolio and worldwide field team, Cadence has the opportunity to accelerate the expansion of the emerging formal analysis sector as more mainstream customers adopt Verification Apps for IP and SoC development.

“Jasper and Cadence serve top-tier customers that will benefit from expanded formal technology and a broader, tightly-integrated verification solution,” said Kathryn Kranen, president and CEO of Jasper. “The verification technologies, when combined, will benefit customers through a comprehensive metric-driven verification approach that unites formal and dynamic techniques, realizing the strength of each and leveraging the integration between them.”

Cadence intends to finance the transaction with available cash and an existing revolving credit facility. The transaction is expected to close in the second quarter of fiscal 2014, subject to customary closing conditions including regulatory approvals. Cadence expects the transaction to be accretive to its non-GAAP earnings per share in fiscal 2015 after the impact of merger-related accounting.  The impact on fiscal 2014 non-GAAP earnings per share will be provided when Cadence reports its second quarter fiscal 2014 financial results.The impact on GAAP earnings per share will be available after the completion of valuation and purchase accounting.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence® software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available atwww.cadence.com.

Leave a Reply

featured blogs
Nov 12, 2024
The release of Matter 1.4 brings feature updates like long idle time, Matter-certified HRAP devices, improved ecosystem support, and new Matter device types....
Nov 13, 2024
Implementing the classic 'hand coming out of bowl' when you can see there's no one under the table is very tempting'¦...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
37,326 views