industry news
Subscribe Now

Accellera Chair Shishpal Rawat Talks about Roadmap for IP and System Design Standards at IP-SOC 2011

Who

Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat’s invited talk on The Roadmap for IP and System Design Standards.

What

The Roadmap for IP and System Design Standards
Shishpal Rawat, Accellera Chair
System, software and semiconductor design activities are converging to meet the increasing challenges of creating SoCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups’ standard activities — IP Tagging, IP-XACT™, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM™) — the benefits of our standards, their fit with SystemC, and the roadmap for adoption.

When/Where

17:15 – 18:45, Wednesday, 7 December, 2011
World Trade Center
5 place Robert Schuman
38 000 Grenoble
France

Information and Registration

To register for IP-SOC, please visit http://www.design-reuse.com/ipsoc2011/registration/.

For more information about Accellera, please visit www.accellera.org.

About IP-SOC

IP-SOC is the leading industry event for the Intellectual Property (IP) and Embedded Electronic Systems community.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera’s partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

For membership information, please email membership@accellera.org.

Leave a Reply

featured blogs
Dec 19, 2024
Explore Concurrent Multiprotocol and examine the distinctions between CMP single channel, CMP with concurrent listening, and CMP with BLE Dynamic Multiprotocol....
Dec 20, 2024
Do you think the proton is formed from three quarks? Think again. It may be made from five, two of which are heavier than the proton itself!...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured chalk talk

Advantech Dual Band WiFi
Sponsored by Mouser Electronics and Advantech
In this episode of Chalk Talk, Amelia Dalton and Monica Goode from Advantech investigate the what, where, and how of dual band WiFi. They also explore the benefits that dual band WiFi can bring to a variety of embedded designs and how you can take advantage of Advantech dual band WiFi solutions for your next design.
Jul 31, 2024
84,017 views