feature article
Subscribe Now

Bigger and Smaller

KLA-Tencor Addresses Both Trends

Things are getting bigger and smaller. It’s the way of technology: two so-far unstoppable trends, one inexorable and much ballyhooed, the other more cautious and halting, but, as yet, undeterred.

The first trend forces me to exercise what, in 2009, I decided to call Moyer’s Law (to crushing silence and no subsequent citations that I can discern): “Every technology-related paper or presentation must mention Moore’s Law at least once to achieve legitimacy.” So, to ensure that you’ll read further, let’s simply get this out of the way: the first trend is Moore’s Law. There, it’s done.

Yes, features are getting smaller.

At the same time, wafers get larger. Back when I spent some time working in a fab right after college, the transition to 4” wafers was well underway. Since then, things have gotten much larger, and they have also switched to the metric system, forcing many of us to do some quick math to figure out just how big 300 mm is.

While everyone assumes features will get smaller, such confidence is not found in the continued increase in wafer size. New equipment is expensive. Bigger wafers are heavier, harder to handle. And heck, for a smaller fabless company, one gimongous wafer could hold a lifetime’s supply of their chips, so volume management strategies must be rethought.

But, at each crevasse between one wafer size and another, after much standing at the edge and mumbling doubts and dithering, eventually we muster the courage to jump across.

So, once again, wafers are getting bigger.

This time it’s 450 mm. (That’s about 18” to us Americans and some Brits… half a yard, 9.1% of a rod, 2.3% of a chain… yeah, that’s a big-ass wafer!) And 450 is now officially the Big Deal in Siliconland. (To the chagrin of other areas being out-shouted…)

Both of these trends place new demands on the equipment in the fab. Each generation of tools seems to get larger and more expensive, meaning fewer guys can afford them, meaning the equipment guys have to be dang sure that the dudes with the deep pockets are going to pony up before spending ungodly sums of cash on development. While less of a question with feature size creep, it’s a bigger gamble with wafer size.

The thing with wafers is that someone has to start the ingot rolling. You can’t manufacture a new wafer size until you’ve proven it out in a pilot line, and you can’t get a pilot line going until there are tools in place, and you can’t build tools until you have wafers to run through the prototypes. And you can’t use those first wafers without being sure that you’re starting with good material.

Which means that the first piece of equipment out the door (after a really big silicon furnace and saw) is a blank wafer inspection tool. For such a prosaic function, there’s a lot riding on it. KLA-Tencor recently announced their Surfscan SP3 450 inspection tool, and I got to take a look at it in their facility. And to address what I’m sure is the first screaming question in your mind right now, yes, I did look silly in that cleanroom getup. No, there are no pictures. Time to move along.

Such a tool accomplishes two things. First, for developing tools, it lets you know what you’re working with – if you have defects on the wafer going in, then you know that the new equipment didn’t cause those defects. More productively, it helps the wafer guys improve the quality of their wafers, which is part of the learning curve with each new size increment.

As an example, KLA-Tencor showed a comparison between 300-mm and 450-mm wafer defects, both at state-of-their-art levels using 45-nm technology. The 300-mm workhorse had 5 defects on it (all of which were small) and was very flat (flatness being extraordinarily important since focal lengths are so short). The 450-mm wafer, by contrast, had almost 4000 defects of all sizes, and it had relatively poor flatness. This is obviously more than pure scaling would suggest, so there’s work to be done on the wafers.

Flatness in particular gets tougher the bigger you get. Gravity is not your friend; sagging is not just for renegade pants. Some forgiveness can be afforded by the wafer chuck itself, which uses vacuum to suck the wafer down, partially smoothing out some flatness issues, but still: pre-Columbian beliefs are welcome here.

To improve their resolution at the 20-nm node and beyond, they’ve moved to deep UV illumination. To be clear, this light wavelength has nothing to do with the exposure wavelength, but rather is the light that’s shone on the wafers to pick up the minute motes that can make for manufacturing mayhem. This reflects a migration from visible light in their original SP1 version to 355-nm UV in the SP2 edition, graduating to 263-nm in the SP3 and SP3 450.

To hedge their manufacturing bets, the new machine actually has two loading stations: one for 300-mm wafers and one for 450-mm wafers. This allows the machine to be used for both wafer sizes, smoothing the transition from one size to the other.

Can you believe we’re really giving this much attention to a machine that simply looks at a blank wafer? But it’s the first in what has to be a refreshed equipment ecosystem for supporting the new wafer size.

Meanwhile, on the Moore side of things, there are various tools that have to maintain stride in the march, including in the metrology department. Prosaic duties like reticle inspection have to keep up (X5.2 and Teron 611 units just announced). But there’s another change that’s come along with the last node or two that’s not incremental: the move to double-patterning.

In the old days (which we’re mostly still in), when we used one mask per exposure layer (and did it while we were knee-deep in snow), one of the important process control steps was inspection of the “overlay” between layers – that is, how well one layer was aligned above the other. This capability uses a registration pattern in the scribe line that looks something like the pattern that your printer may put out when you put a new ink cartridge in. In order to inspect this, a special etch had to be done to open up the layer below so that it and the upper layer could be inspected at the same time.

With double-patterning on the most critical layers, it’s no longer enough to view two layers. Now you have to make sure that both patterns of one layer overlay properly and that, together, they overlay correctly above the prior pair of patterns. If you did only one pair at a time, then too much error might accumulate as you went up the stack.

Part of what makes this difficult is the use of newer materials that are harder to see through. This is why you’ve had to clear out the materials for measurement in the past. For the new Archer 500 overlay inspection system, KLA-Tencor has broadened the wavelength of exposure light, which lets them see through many of these materials. As a result, they can look through the photoresists and hard masks to take the measurements. This eliminates an entire etch sequence – that’s a big deal.

So no matter whether you’re going bigger or smaller, you’re going to need new equipment either way. Not sure if that’s a win-win or a can’t-win. But no matter which, big bucks will be going into both of these directions.

 

More info:

Surfscan SP3 450

X5.2, Teron 611

Archer 500 

2 thoughts on “Bigger and Smaller”

  1. Just checked – a 450mm wafer is the equivalent of around 21 of the 4 inch wafers that we both remember fondly – or even more roughly one 450 wafer is the same as a compplete lot of 4 inch wafers

Leave a Reply

featured blogs
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....
Apr 18, 2024
Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. V...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Switch to Simple with Klippon Relay
In this episode of Chalk Talk, Amelia Dalton and Lars Hohmeier from Weidmüller explore the what, where, and how of Weidmüller's extensive portfolio of Klippon relays. They investigate the pros and cons of mechanical relays, the benefits that the Klippon universal range of relays brings to the table, and how Weidmüller's digital selection guide can help you choose the best relay solution for your next design.
Sep 26, 2023
25,888 views