Semiconductor technology just gets curiouser and curiouser as feature sizes shrink. In real life, that means that EDA tools have to work harder and harder to figure out what’s going on and help engineers implement enormously complex designs. As usual, the problem can be boiled down to things that didn’t use to matter becoming a problem.

Of course, at the extremely tiny level anticipated by technologies like carbon nanotubes, things change completely. But that’s still research. Leading-edge designs today are still using “conventional” processing, but making a real design work isn’t easy.

According to Cadence, Samsung approached them for help at 28 nm; Cadence then essentially used Samsung as a lead customer to work out real-world issues for the next nodes, running test wafers and measuring the results so they could tune the tools. While different fabs will operate somewhat differently, this gave them modeling constructs that could be customized so that they weren’t Samsung-only results.

There are two themes running through their improvements, and they’re typical for the kinds of things happening in EDA over the last year or two. The first is simply (although that might be a poor choice of words) improving models to account for previously negligible effects.

The second lies in taking elements of what used to be batch analysis after a design is done and moving them into the design loop itself to reduce the number of iterations. So, for instance, instead of running a batch parasitic extraction process when layout is complete, the extraction engine can be employed during layout so that issues can be found for real-time correction while the design is underway.

Wilbur Luo, Cadence’s Silicon Realization Group Director of Product Marketing, outlined three areas where design issues were identified; these issues focused their tool enhancement efforts. The areas were lithography process check (LPC), chemical-mechanical polishing (CMP), and layout-dependent effects (LDE).

The primary LPC issue is one we’ve talked about already: pattern matching. Design rules have become too complex to manage by old-fashioned design rules, and model-based approaches are too slow for anything except device and cell testing. So pattern matching is now hitting its stride as an important way of banning layouts that will hurt (or outright kill) yields. This allows much more flexibility for rules that need to encompass complicated geometric and spatial considerations.

There are, in fact, many patterns that must be managed. Cadence provides foundries with a tool that lets them classify patterns, grouping the similar ones. As a given process becomes more mature, any ongoing learning can be worked into what is essentially a living library of patterns. In addition, a design house may learn some tricks of their own that they don’t want to share with their competitors, so they can include their own proprietary patterns in what amounts to a private corner of the library.

Pattern matching can be run live as the design is being created. Of course, this matters most for custom design, since the feedback can be used immediately by the layout designer. But automatic place and route can also take advantage of it: presumably each cell will be clean, but, as cells come together, you must still work to avoid unworkable effects at the edges.

CMP brings a separate set of issues, especially since copper layers are becoming thinner. CMP accommodations have been needed for a long time simply because the grinding process doesn’t occur uniformly across a wafer. Modeling CMP has moved from the assumption that the pad was uncompressible, grinding only the high spots, to far more elaborate models that take into account the various time-changing rates of material loss on different parts of a die as the grinding proceeds and as the pad and “consumables” (i.e., the slurry) are used up.

CMP is used both on oxides between layers as well as on copper in “damascene” processes, where copper is nestled into oxide slots like so much delicate inlaid filigree. Especially with copper CMP, you have a number of issues thinning the copper. The grinding process itself is non-uniform, and the fact that the wafer doesn’t even start out perfectly flat means that you’re faced with miniscule bumps and valleys on a scale much smaller than the width of the grinding pad.

As we discussed a while back, metal fill is used to minimize huge changes in the layout density of metal, but further optimization is needed. Cadence allows for analysis after the initial fill is in place in order to tweak the fill and feed the parasitics back into the simulation so that the effects of CMP are incorporated into performance calculations.

This analysis can be done during the design of a block rather than awaiting full chip assembly. The tool will need to look as far away as 100 µm as it gauges the metal density; a chip floorplan allows neighboring blocks to be included in the analysis. Of course, it won’t be final until all the blocks are in place for a last scrub.

LDE issues relate to the impact that neighboring circuits, whether or not related, have on each other. Again, the internal guts of a standard cell can be hand-tweaked until all is copacetic, but those cells will end up abutted to other cells, and that’s where unintended problems can arise. This concept isn’t new, having started at the 40nm node, but the types and level of interaction continue to grow. Historically, cells have been over-spaced just to keep things safe, but the resulting area penalty is becoming unacceptable, so the EDA tools have to take the issue head-on.

For custom design, you can run analysis that will both identify problems and back-annotate results to SPICE. Unlike pattern matching, you can’t reach across block boundaries in a floorplanned design, but you can do what-if trials to explore different ways of addressing issues, since fixing one thing may introduce something new.

For digital designs, some cells simply may not play well together. So you can mark them as not allowed to be placed next to each other (you can also mark them as allowed). In addition, the placer can flip cells or add spacers to reduce interactions.

All in all, it’s a motley set of issues, identified and prioritized through Samsung’s collaboration. But they expect these to be the key issues at the 28nm node much more generally; the parameters and coefficients used in the models will be adjusted for each fab. And they will hopefully be flexible enough to accommodate the issues that will arise as things get yet curiouser at the next node. Although they won’t know that for sure until they start running test lots at some other lead foundry.

Photo (detail): Dennis Jarvis/Flickr