editor's blog
Subscribe Now

A Jump in EUV Resist Sensitivity

There was an interesting presentation that happened towards the end of SPIE Litho – it seemed to catch the audience off guard, and I frankly went away with the sense that there was some confusion in the room.

The presentation discussed an experiment that was done at Osaka University as part of the overall effort to optimize EUV exposure. It all relates to this seemingly inviolate triumvirate of “RLS”: resolution, LWR (line-width roughness), and sensitivity. Improvements within these three have to come at the expense of something within these three – they form a zero-sum game.

Normally, you expose the photoresist through the mask for the entire length of the exposure. The photons create acid where they interact with the resist, and this acid provides for the selective removal of resist material during development.

This experiment changed that. The exposure was broken into two steps:

  • A short exposure through the mask
  • After 10-15 minutes, then, with no mask, just a flood of UV across the entire wafer.

The first exposure seemed to create some acid, but mostly “sensitized” the photoresist (and I frankly didn’t come away understanding what that “sensitizing” meant from a chemical standpoint). The strange thing then was that flooding with the second exposure created the normal amount of acid only in the sensitized area.

This provided about 9 times the prior sensitivity, with no apparent tradeoff in LWR or resolution.

Note that no special resists were used; these were the same resists as are currently being used.

I didn’t get the sense that they had a real handle on what the underlying mechanisms were, and it was surprising to the audience. Assuming the data are correct, it’s certainly an interesting result. We’ll have to see if anything further comes of it, or if it goes the way of cold fusion…

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Infineon and Mouser introduction to Reliable Solid State Isolators
Sponsored by Mouser Electronics and Infineon
In this episode of Chalk Talk, Amelia Dalton and Daniel Callen Jr. from Infineon explore trends in solid state isolator and relay solutions, the benefits that Infineon’s SSI solutions bring to the table, and how you can get started using these solutions for your next design. 
May 28, 2024
36,498 views