Going Expensive to Reduce Interposer Cost
November 11, 2013
Imec has been working 2,5D IC issues with a particular focus on optimizing costs and, in particular, test yields. Yields can take what might have been straightforward-looking cost numbers and make things not so clear.
In their work on interposers, Eric Beyne took a look at three different ways of routing the signals from a wide-I/O memory. These puppies have lots of connections – like, 1200 per chip. He … Read More → "Going Expensive to Reduce Interposer Cost"
