editor's blog
Subscribe Now

Laying n-Type Epi

Dopants used to be there just for their doping. But stress is now an important aspect as well, which means the dopant atoms must be sized appropriately as compared to their silicon hosts. This has worked for p-type, where compressive stress is desired. Germanium, which is larger than silicon, compresses the silicon, increasing hole mobility.

n-type should be the reverse: tensile stress is needed, meaning smaller dopant atoms. Phosphorus and carbon are both smaller and can work. Sounds simple, right?

Well, apparently not so. The n-type dopants have a tendency to migrate, and so far increased border security hasn’t worked. OK, kidding. About the security, that is. The migration has remained to be solved.

At Semicon West, Applied Materials announced that they had found a way to create a stable n-type epi layer. How do they manage it, you ask? Keep asking… they’re not telling. There was a mention of millisecond anneals helping to tweak any vagabonds before they get too far. And whatever they do sets up a strict thermal budget, although not so low that it affects the back-end interconnect processing.

Details aside, if this is all working as promised, then we have more control over how to optimize the performance of n- and p-type devices. You can read more in their release.

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
39,175 views