editor's blog
Subscribe Now

Simpler CDC Exception Handling

For static timing analysis, it’s a concept that goes back years. You get a bunch of violations, and then you have to decide which ones represent false paths or multi-cycle paths and create “exceptions” for them. Tedious.

Well, apparently formal analysis can have the same issue. Only here they’re referred to as “waivers,” according to Real Intent. If you run analysis and get a long list of potential violations, you have to go through the list and, one by one, check them for “false positives” and mark them as such. Time-consuming and error-prone. And tedious. Especially when working on large-scale SoCs (so-called “giga-scale”).

In their latest release of Meridian CDC, which does clock-domain crossing verification, Real Intent has provided a different way of handling this: provide more granular control over the run parameters in the form of rules or constraints that can be successively refined.

Using the old method, if a particular over-reaching aspect of analysis caused 100 false positives, you’d have to find all 100 and “waive” them. With the new approach, when you find the first one, you make the refinement, and then, with a rerun of the analysis, the one you found and the other 99 all disappear. OK, not disappear per se, but they’re grouped together as not being an unexpected finding. You can also review that list to make sure nothing snuck through. (This is a simplification of a more sophisticated overall process, but it captures the essence.)

This may take some iterations, but in the end, you can have a clean run with no exceptions, and the way you got there is less likely to have involved a mistake here or there.

You can find out more about Real Intent’s latest Meridian CDC release in their announcement.

Leave a Reply

featured blogs
Nov 22, 2024
We're providing every session and keynote from Works With 2024 on-demand. It's the only place wireless IoT developers can access hands-on training for free....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Machine Learning on the Edge
Sponsored by Mouser Electronics and Infineon
Edge machine learning is a great way to allow embedded devices to run applications that can collect sensor data and locally process that data. In this episode of Chalk Talk, Amelia Dalton and Clark Jarvis from Infineon explore how the IMAGIMOB Studio, ModusToolbox™ Software, and PSoC and AURIX™ microcontrollers can help you develop a custom machine learning on the edge application from scratch. They also investigate how the IMAGIMOB Studio can help you easily develop and deploy AI/ML models and the benefits that the PSoC™ 6 Artificial Intelligence Evaluation Kit will bring to your next machine learning on the edge application design process.
Aug 12, 2024
56,196 views