The recent edition of ICCAD provided an interesting look at what some of the contenders will be for logic switches once our standard configurations are no longer viable. Just to put things into perspective, FinFETs are old-tech in this timeframe.
One of the proposals stopped short of departing silicon: a silicon nano-wire FET. Imagine your standard Montana barbed-wire fence: three strands of wire between two posts. Now imagine that it snowed, and some kids piled up the snow like a wall running between the two fence posts so that the barbed wire strands were surrounded by snow.
Now shrink the scene dramatically, replace wire with silicon nano-wires with an oxide coating, and replace the snow with poly. The fence posts on either end are the source and drain. Now the poly acts as a gate; the nano-wires are the channel(s). This configuration even earns its own acronym: GAA, for gate all around, since the wire/channel is completely surrounded by the poly gate.
The benefits are, first, improved Ion/Ioff performance. Additionally, the ability to go vertical can save space: while a standard inverter needs a bigger p-channel device than n-channel device, increasing the area used, this compensation can be done vertically instead of horizontally. You can also surround different nano-wires with different gates on the same transistor for more complex control.
The downside is slower speed as compared to planar transistors; running a double-stack can help (at the expense of area, of course). Strain is also very helpful in improving performance.
Of course, everyone talks about carbon nanotubes – CNTs – (or their unrolled counterparts, graphene sheets) as having a role in the future. We’ll cover some of the issues involved in building CNTs in a separate piece shortly.
One of the presentations featured an “ambipolar CNTFET”. It features one or more CNTs between the source and drain with a back gate in the substrate. The term “ambipolar” refers to the fact that it can work with either a positive or negative VT according to the doping at the ends of the CNT.
One configuration has a double-gate, with one of the gates setting the device polarity – switching it between n-type and p-type on the fly. An inverter built out of these can act more like an XOR gate if the polarity gate is exercised. And the good news here is that the p-type and n-type conductance are equal, and the doping step (to set the polarity in a single-gate version) isn’t required in the double-gate configuration.
Memristor FETs were also discussed; these can be used for memory, switching, and sensing. They’re odd beasts, a sort of “missing device” that we will discuss in more detail in a future piece.
Finally, we got a look at a theoretical switch – one that hasn’t been built yet. It’s called a bilayer pseudospin FET, or BiSFET. It has only been simulated to this point. It’s built out of two layers of graphene separated by a small tunneling gap. Each sheet has a gate on the side opposite the gap.
Following math that resembles that of electron spin, the concept here is that an exciton condensate should form between the two layers. This many-body tunneling phenomenon should switch on at about 25 mV – a very low VT. Whether that happens and how stable it is has to be demonstrated in real life. Even if the condensate itself doesn’t form, single-body tunneling would be possible, but the VT would increase to 100 mV from 25 and the power would increase by about 10x.
Another challenge to this approach is that you need a clocked power supply or else the output of a gate will stick to its value.
Increasingly strange-looking devices as we delve deeper and deeper into a quantum world…
