The recent edition of ICCAD provided an interesting look at what some of the contenders will be for logic switches once our standard configurations are no longer viable. Just to put things into perspective, FinFETs are old-tech in this timeframe.

One of the proposals stopped short of departing silicon: a silicon nano-wire FET. Imagine your standard Montana barbed-wire fence: three strands of wire between two posts. Now imagine that it snowed, and some kids piled up the snow like a wall running between the two fence posts so that the barbed wire strands were … Read More → "What Will the Next Logic Switch Look Like?"

While the recent MEMS Executive Congress focused on electro-mechanical applications, occasionally MEMS processing techniques were highlighted for strictly electrical purposes, with no mechanical component.

In one example, ICEMOS talked about their collaboration with MEMS manufacturer Omron for a new way of making superjunction power transistors.

Superjunction transistors overcome the R_on/breakdown tradeoff issue using alternating p and n stripes. In theory, these can be arranged a number of different ways, but, according to ICEMOS, the typical way it’s done now is horizontally, by growing a series of epitaxial layers of … Read More → "Another Transistor Goes Vertical"

Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.

But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t … Read More → "A Different TSV"