editor's blog
Subscribe Now

Your Standard Merger

Last week OSCI and Accellera decided to join forces. To some extent, this might be viewed as the union of the abstract and the concrete. OSCI lives in the world of SystemC and TLM; much of what Accellera does is further down the abstraction stack (although UVM shows that Accellera was already moving up). 

To some extent these are two different worlds (when discussing verification recently with someone, I mentioned TLM… and got looked at like I had grown a second head because the person lived in the concrete pre-mask verification world). But if the vision of abstract-architecture-refined-to-finished-chip is to be realized, it can help to do that within a single body.

Minor details – like what the combined entity will be called – have yet to be worked out. The end of the year is pegged as the target for all such niceties.

This largely leaves Si2 as the other pre-IEEE standards body. Having two such entities ensures that it will still be possible to take two competing proposals from two competing companies and create two different standards through two different bodies*, both of them legit.

That’s SOP.

More in their release

 

*Scroll to the last section…

Leave a Reply

featured blogs
Nov 15, 2024
Explore the benefits of Delta DFU (device firmware update), its impact on firmware update efficiency, and results from real ota updates in IoT devices....
Nov 13, 2024
Implementing the classic 'hand coming out of bowl' when you can see there's no one under the table is very tempting'¦...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
80,240 views