Big companies have divisions. Big EDA companies have synthesis divisions and design-for-test (DFT) divisions.
Clearly the two have nothing to do with each other. They’re different technologies applied at different times in the flow.
So why in the heck would Oasys, a synthesis company (not big enough yet for divisions) announce DFT support? Sounds like a classic distraction, trying to do too much.
Actually, that’s not how they see it. In fact, since most DFT hardware can be described in RTL, you can presumably do a better job by including it early on.
They claim that their angle is the fact that they do “chip synthesis,” not “block synthesis.” Test structures are a chip-level consideration, not just for any block. Traditionally, you may have to do block-level DFT and piece it together, but that’s usually done after the main functional logic has been synthesized. So debugging at the netlist level can be really tough.
Prior to synthesis, they can also analyze the chip to make sure it’s “DFT-ready,” looking for things like fully-controllable clocks, sets, and resets. Secondarily, they can also check whether the logic is ATPG-friendly.
They don’t do their own compression, but can integrate in various third-party compression schemes as well as AMS analog blocks that already have scan chains built in.
More details in their release…
