June 2011 – EEJournal

The Old Switcheroo

June 30, 2011

Way back in 2004, during the Vice Presidential debate, Dick Cheney urged listeners to go to “factcheck.com” to confirm that the campaign spin-checking organization would back him up on some facts.

Only one problem: the correct site was “factcheck.org.” The domain “factcheck.com” had nothing on it. Overnight, the factcheck.com site got redirected to George Soros’ blog, an unlikely place to find validation of Cheney.

Presumably, Republicans would think this a dirty trick, Democrats would think it clever. Right or wrong, you can’t help … Read More → "The Old Switcheroo"

Tracking the Envelope

by Amelia Dalton

June 29, 2011

For the last couple years, “envelope tracking” has caught on as a way to reduce power in phones, cellular base stations, and digital broadcast transmitters. The idea is that RF power amplifiers are most efficient when the signal amplitude runs near the drain voltage, operating in or near saturation or “compression.” When the signal isn’t running that high, then, with a constant power level on the amplifier, the remainder of that power is wasted as heat.

With envelope tracking (ET), the signal envelope is detected and fed to a power modulator … Read More → "Tracking the Envelope"

Your Standard Merger

by Bryon Moyer

June 27, 2011

Last week OSCI and Accellera decided to join forces. To some extent, this might be viewed as the union of the abstract and the concrete. OSCI lives in the world of SystemC and TLM; much of what Accellera does is further down the abstraction stack (although UVM shows that Accellera was already moving up).

To some extent these are two different worlds (when discussing verification recently with someone, I mentioned TLM… and got looked at like I had grown a second head because the person lived in the concrete pre-mask verification world). But if the … Read More → "Your Standard Merger"

Scenarios – Certain and Less So

by Amelia Dalton

June 24, 2011

Feeling somehow less worthy in the shadow of the passing of Bob Pease… (with no offense intended towards Docea…)

I spent a few minutes with Docea at DAC a couple weeks ago. You may recall their Aceplorer product dealing with both power and thermal analysis. Two things caught my eye, one of which is a new feature, the other something they’re working on.

The new feature is scenario generation. This is particularly applicable to multi-mode designs, where different modes are exercised as different … Read More → "Scenarios – Certain and Less So"

This is the Bob Pease I remember

by Amelia Dalton

June 23, 2011

About three years ago I had a lunch with Bob Pease. For years I had read his column, agreeing with much of what he said and disagreeing, sometimes to the point of yelling at the page, with some of what he said. Bob created a role for himself, and grew the role – grouch, perhaps even curmudgeon, larger than life, analog guru, pragmatist, and puncturer of bubbles of bogosity. Himalayan walker and VW … Read More →

Is That Any of Your Business?

by Jim Turley

June 22, 2011

Big companies have divisions. Big EDA companies have synthesis divisions and design-for-test (DFT) divisions.

Clearly the two have nothing to do with each other. They’re different technologies applied at different times in the flow.

So why in the heck would Oasys, a synthesis company (not big enough yet for divisions) announce DFT support? Sounds like a classic distraction, trying to do too much.

Actually, that’s not how they see it. In fact, since most DFT hardware can be described in RTL, you can presumably do a better job by … Read More → "Is That Any of Your Business?"

Sorting Through the Rubble

by Jim Turley

June 21, 2011

Roughly a year ago we talked about Vennsa’s OnPoint tool for identifying what went wrong during verification when something goes wrong. I got an update at DAC recently, where they talked about two concepts they’ve brought to their technology in order to make it easier to decide what to fix when there’s a problem.

The first is that of triage, which automatically tries to combine different failures if they appear to have the same root cause. Prior to this, … Read More → "Sorting Through the Rubble"

Custom Chip Planning

by Kevin Morris

June 16, 2011

Digital designers have had semi-automated design flows for a long time; custom and analog designers, not so much.

Pulsic recently announced that they’re taking some of the custom EDA technology they’ve had for ten years, combining it with new technology, and integrating it into a flow as their Pulsic Planning Solution. I got a chance to talk to them about it at DAC.

Their solution consists of four components:

a hierarchical floorplanner, the Unity Chip Planner;
a power grid planner, the Unity Power Planner, which can … Read More → "Custom Chip Planning"

Chip Design Tweaker

by Kevin Morris

June 15, 2011

Last-minute chip design changes are always unfortunate, whether right before cutting masks or, worse yet, after you get silicon back. Some major tool environments provide engineering change order (ECO) support, some don’t. But it’s always a less-than-perfect scenario: an ideal top-down flow would maintain the chain of refinement from the most abstract representation down to the final details. Making a change only at the low level breaks that.

But the practical fact is that, if you’ve spent weeks and months getting things just the way you want them – with the … Read More → "Chip Design Tweaker"

Another Way to Test Your 3D ICs

by Jim Turley

June 14, 2011

A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.

More info in their release…

… Read More →