When Imec and Atrenta recently announced a design flow for planning and routing signals between different stacked ICs, I thought, “Wait, I’ve seen this before, with a different name.” I wrote about Javelin’s role in this process a couple years ago. And it occurred to me that Javelin had been pretty quiet, and maybe I’d missed an acquisition or something.

So I checked the website – at first glance, everything seems in order. Then I … Read More → "A New 3D IC Manager"

A couple years ago, in an article about clock-generated noise, we talked about Teklatech’s power-shaping feature, which, at the time, was designed to smooth out the noise spectrum by making as few clock edges coincident as possible. Well, they’ve just released a new version that provides more control over the spectrum: you can design in what you want.

In conjunction with new multi-mode, multi-corner (MMMC) support, you can actually optimize different modes for different spectra concurrently by focusing in on the key noisy … Read More → "Allocating Spectrum"

As flexible as FPGAs are, you would think that you could stuff debug logic in there to probe around the internals and figure out what’s going on when you’ve got a problem.

And, if you’ve been paying attention, you’d say, “Yeah, Altera’s SignalTap and Xilinx’s ChipScope have been doing that for years.”

Well, Springsoft has just announced a ProbeLink product that sounds remarkably similar. What’s different?

The primary low-level differences are the following:

–  & … Read More → "Take it Outside"

Each new communications protocol adds to the complexity of its predecessor, and the 3GPP-LTE cellular standard is no exception. According to Synopsys, there are more than a thousand tests specified in the standard to ensure compliance.

And it’s actually twice that bad: before you cut a chip, you need to verify the design against those tests. Then, when the chip comes out, you need to verify the actual silicon against the same tests.

For this reason, Synopsys – maker of pre-silicon design tools – and Rhode & Schwarz – maker of post-silicon, real, … Read More → "Quicker LTE Validation"

You may recall a while back – actually, a good while back – we looked at parasitic extraction tools and contrasted the field solver approach with Silicon Frontline’s random-walk approach. Reprised really briefly, with the random walk approach, rather than dividing the entire structure up into chunks and solving the whole thing, you follow lots of random paths through dielectric until you hit metal, and, statistically, you end up with the precision needed to determine the parasitics in all three dimensions.

As with all such … Read More → "Stop Repeating Yourself"