Security: Hard and Soft

Next Up: A Tortoise That Checks Your Chip for Flaws

by Jim Turley

I hate writing about security. I hate it because I wish it were unnecessary. There was a time when engineering meant making a product that did what you wanted it to do. Now it means spending a bunch of time making it not do what other people want but you don’t want. This sucks.

Most of the problem with implementing security features is guessing where the vulnerabilities are. How do you fix a bug you’ve never even thought of, much less identified? At least “real” hardware bugs are unintentional. Security hacks are both deliberate and malicious. Someone is trying to break your stuff.  Read More


latest news

February 23, 2017

VadaTech launches a dual-channel IF signal conditioning unit

New Bidirectional Power-Switching Solution is One of the Industry’s Smallest

February 21, 2017

DDC-I Announces SafeMC RTOS Technology on Xilinx Zynq UltraScale+ MPSoC Multicore Devices

February 16, 2017

Anritsu Redefines Microwave and mmWave Measurements with Introduction of the Ultraportable Spectrum MasterTM Family

February 14, 2017

Lighter and Faster Connectivity Solutions for Defense Systems

February 13, 2017

Current-Sensing High-Voltage Contactor Offers Power Switching Solution

February 09, 2017

Vishay Intertechnology Extends Capacitance Range of MIL-PRF-39006/33-Qualified Wet Tantalum Capacitor

February 08, 2017

Saelig Launches New Ultra-Low Jitter Oscillators

January 31, 2017

SP Devices launches the world’s first 14-bit digitizer with 10 GS/s sampling rate

TE Connectivity’s Next Generation Composite Connectors Provide Rugged Reliability in Harsh Environments

January 25, 2017

Pentek Announces 8-Channel A/D Jade XMC Module for Defense and Radar Phased-Array Applications

Intepro’s New Programmable AC Power Source Includes DC Output Capability

January 24, 2017

Curtiss-Wright Leads the Embedded Market in Bringing Gen 4 PCIe Capability to Standard VPX

January 23, 2017

Curtiss-Wright Debuts Industry’s First COTS Data Storage System to Support 2-Layer Encryption for Protecting Classified Data-at-Rest

MilAero News Archive

High Speed Wizardry and a Steaming Cauldron of VPX Fixins

Hoodoo Rituals for New Technology Implementation

by Amelia Dalton

“Swimming in Sensors, Drowning in Data”

Mil-Aero Challenges Go Mainstream

by Kevin Morris

Making COTS Real

VITA Embedded Tech Trends

by Kevin Morris

Security and Safety

Not Independent Considerations

by Bryon Moyer

Microsemi Tackles RISC-V

Open Architecture FPGA Processor Core

by Kevin Morris

MilAero Article Archive

 

Editors' Blog

A More Secure Time Server

posted by Bryon Moyer

Time servers allow us to track multiple events from different systems and networks with a consistent time base. But an evildoer can flood such servers with requests, causing crashes. Microsemi has released a new time server that addresses this vulnerability. (13-Jan)

Driving ADAS

posted by Dick Selwood

ARM is working to provide support for safe automotive systems (23-Apr)

Requirements Modeling and Simulation

posted by Bryon Moyer

Argosim’s new STIMULUS tool is intended to make sure requirements are solid before someone starts building from them. (2-Apr)

How Does Multicore Affect Code Coverage?

posted by Bryon Moyer

Analysis tools can help identify whether code gets executed. LDRA recently added multicore coverage; what does this mean? (7-May)

Model-based Product Line Engineering

posted by Dick Selwood

(20-Mar)

MilAero Editors' Blog Archive

forum

Radio FPGA!

Posted on 02/23/17 at 12:48 AM by TotallyLost

TotallyLost
Thanks Kevin --- way cool parts --- can not wait for their general availability smiling

FPGAs Race for the Bottom

Posted on 02/20/17 at 4:42 PM by logos

CyrilJ,

You're links are broken.

Also, Microsemi's THREE separate software suites are INCONSISTENT with Linux support.
- FlashPro for Libero IDE does not support Linux. Microsemi's site and documentation is all over the place with FlashPro hardware…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 2:13 PM by TotallyLost

TotallyLost
What is FAR worse?

An 8-way time division multiplexor to "fairly share" memory between 6 processors and 2 DMA channels -- no priority accesses to starve another channel, no contention based allocations, just straight channel 1 gets only time slot 1, ch…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 1:16 PM by TotallyLost

TotallyLost
Now you might say that no one would be that stupid as to pack all accessed data into a single subchannel. With the number of sub-channels being 2^n (where n is 1, 2 or 3), it's also pretty likely that the underlying data structure to be processed will hav…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 12:37 PM by TotallyLost

TotallyLost
@Karl -- sure multiple banks/channels can offer concurrent read/write, or even multiply sourced reads/write -- but each channel still has the native single access or burst fill performance timings.

Now look at the last three figures above, where Cadenc…

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