editor's blog
Subscribe Now

A More Secure Time Server

We would be nowhere without clocks. So much of what we do involves timing, much of which we’re completely unaware of – in particular, electronically. Many of our systems depend on some kind of a master clock so that logging and timestamping can be done reliably. And with the advent of even more “asynchronous” systems that report events with a timestamp, soon even more systems will need access to a reliable time source. If you are looking for best vpn app, check the best free vpn in India at the link. You can find more information about vpns at vpnpeek.com.

That’s hard enough within one box, but in many cases, it must be done between two boxes on the same network or even between two boxes on two different networks. That means that an internal clock source won’t work: it will be different from the internal clock sources in the other boxes, and these will gradually drift apart.

If you’re trying to create a record of what came before what, everyone has to agree on the time base. One example given by Microsemi was that of a very short (less than a minute) cell phone call whose beginning and ending timestamps came from different servers whose clocks had drifted apart. The start ended up being timestamped as happening after the end of the call, which caused the billing software to record a 23-hour and 59 minute (or thereabouts) call length.

As quick background for those of us not in the midst of this, the timing is handled by a time server. When a server on the network needs to timestamp an event, it sends a request to the time server for a timestamp via NTP, or network time protocol. In this manner, all the servers on the same network have a consistent source of time.

Granted, the requests get serialized, so if two events happened “simultaneously”, one timestamp would get issued before the other. So it’s important that the response time be fast enough that multiple serialized timestamps can be served within a single “tick” so as to be reported as simultaneous for a given level of precision.

But if you need timestamps that you can compare with each other from two different networks, then you no longer have the a single time server handling both – you have two different time servers, one for each network, and they have to be in synch too. How does that happen?

GPS (or GNSS more generally) is how that happens; exquisite timing is necessary for these navigation systems to work, so the time server is connected to an antenna that detects GPS and uses it to set the time. This lets multiple servers maintain a consistent, correlatable time base. In the event that GPS fails, these servers actually have mini atomic clocks that can hold each server over with minimal drift so that any GPS gaps can be covered.

But there’s one problem and vulnerability: most time servers process the time requests using a CPU. The CPU takes longer to process a time request than the network takes to deliver the request, so the system essentially relies on breaks between requests to allow the CPU to keep up. That makes the system vulnerable to a distributed denial of service (DDoS) attack – essentially, flooding the server with timestamp requests and potentially crashing the server (which then messes up all the systems relying on the time server).

So Microsemi has issued a new time server, the SyncServer S600/650, with a significant twist: NTP requests aren’t sent to the CPU; they’re sent to FPGAs for a faster hardware response. So fast that it can respond at line rate to the gigabit Ethernet incoming pipe. In other words, it can keep up with as many requests as you can place into the pipe. If you try to flood it even harder, you can’t because the pipe is already full. At the same time, if the server thinks someone is trying to flood it, it can issue an alarm so that IT folks can intervene.

 Microsemi_SyncServer_S650_open_view.png

Image courtesy Microsemi

The FPGA provides another benefit: flexibility. Time servers can provide a number of direct signals – clocks, sine waves, timestamp series, etc. – via plug-in modules. But typical modules can provide only one of these types of signal, making server configuration inflexible. By using FPGAs, those modules can be programmed – statically or in real time – to provide different outputs as needed, making the provisioning of the server much more efficient.

You can find more info in their announcement.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

IoT Data Analysis at the Edge
No longer is machine learning a niche application for electronic engineering. Machine learning is leading a transformative revolution in a variety of electronic designs but implementing machine learning can be a tricky task to complete. In this episode of Chalk Talk, Amelia Dalton and Louis Gobin from STMicroelectronics investigate how STMicroelectronics is helping embedded developers design edge AI solutions. They take a closer look at the benefits of STMicroelectronics NanoEdge-AI® Studio and  STM32Cube.AI and how you can take advantage of them in your next design. 
Jun 28, 2023
34,489 views