chalk talk
Subscribe Now

De-Risk Yield Manufacturing Ramp-up with Veloce DFT App

Get DFT off the critical path on your next chip design. In this episode of Chalk Talk, Amelia Dalton chats with Jean-Marie Brunet of Mentor Graphics about how you can use emulation to significantly improve your DFT productivity. 

Click here to download a whitepaper entitled “Accelerating Design-For-Test Pattern Simulation.”

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....