New devices that combine the power and flexibility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.
Click here to download a free whitepaper entitled “Architecture Matters: Choosing the Right SoC FPGA for Your Application.”
The “memory performance” comparison in that whitepaper was most likely produced by running an outdated kernel configured with background processes for the “red” line. It also employed faulty analysis on a benchmark that they apparently didn’t understand.
Both the “blue” and “red” SoCs use the same Cortex-A9 and L2 cache controller. Therefore When dataset is smaller than L1D and L2, respectively, both chips should (and actually do, if configured correctly) show exactly the same memory performance. It has nothing to do with DRAM controller or speed.
The fact that Altera engineering/marketing would trumpet a false result, without further investigation, in their whitepaper, shows either incompetence or deceit.
For the LMbench memory benchmark tests, the latest Linux kernels were used at the time the benchmark was taken. The tests were run “out-of-the-box” with no optimizations on either system.
For the L2 cache controller, there are different implementation options available. One of these options is the connection of the snoop control unit (SCU) ports. As explained in the video, one chip routes both SCU ports to the L2 cache; the other routes one SCU port to the L2 cache and one to the on-chip-memory (OCM). A classic architectural tradeoff! One can choose between higher L2 cache or OCM performance. The Altera architects choose higher L2 performance.
In the video, it does explain that the DRAM controller only affects the larger data sets which go beyond the L1 and L2 cache (512 KB). In that case, it is quite remarkable that the SoC with the 400 MHz bus can meet or exceed the performance of the SoC with a 533 MHz external memory bus. This is why the DRAM controller is emphasized in the white paper and the video.
Thank you for your comments. If you watch the video (5:07 to 11:53), I think you will find that it more fully explains the memory subsystem architectural differences and sections of the memory benchmark curve.