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August 22, 2014

Verification Made Easy with Memory Models

by Amelia Dalton

In this week’s Whiteboard Wednesday video, Tom Hackett explains memory models and their role in verifying memory interfaces in today’s SoCs. He’ll explain the differences betweeen memory models and simulation VIP, and talk about how they can help make verification a little easier. Learn more about Cadence IP at http://ip.cadence.com. 

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