Elk Grove, Calif., April 11, 2017 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that IEEE 1800.2™ Standard for Universal Verification Methodology (UVM) has been approved by the IEEE Standards Association (IEEE-SA). The standard will be available for download later this spring at no charge under the Accellera-sponsored IEEE Get Program.
About IEEE 1800.2
The IEEE 1800.2 Standard for UVM establishes a set of Application Programming Interfaces (APIs) that are used to define a base class library (BCL) definition which engineers employ to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard. The goal of the IEEE 1800.2 standard is to improve productivity for electronics systems development by making it easier to verify design components with a standardized verification representation that can be used with various automation tools, helping to lower development costs and improve design quality.
“The UVM Working Group has done an outstanding job developing UVM 1.2 over the past eight years and successfully transferring it to the IEEE,” commented Lu Dai, Accellera Chair. “Now that it is an approved IEEE standard, the Accellera UVM Working Group will continue to provide improvements to the base class library implementation and updates to the UVM User’s Guide. The UVM Language Reference Manual will become responsibility of IEEE, where many key members of the Accellera UVM Working Group also participate.”
“As a world class standards development organization, our mission is to provide a high quality, market relevant standardization environment,” stated Konstantinos Karachalios, managing director of IEEE-SA. “Our partnership with Accellera helps us to provide even more standards to the design automation industry reaching design engineers around the globe.”
Accellera-Sponsored IEEE Get Program
Since its inception in 2010, the Accellera-sponsored IEEE Get Program has resulted in more than 83,000 downloads, providing pre-paid access of electronic design and verification standards to engineers and chip designers worldwide. IEEE 1800.2 will be released under the IEEE Get Program as soon as it is published.
About UVM
In development for more than eight years, UVM has achieved industry-wide success as the standard used by verification engineers to verify complex designs. As an important companion to SystemVerilog, it improves interoperability and reduces the cost of IP development and reuse for each new electronics project. UVM has a very active worldwide user community and forum and its LinkedIn group has almost 7,000 members.
About IEEE-SA
The IEEE Standards Association, a globally recognized standards-setting body within IEEE, develops consensus standards through an open process that engages industry and brings together a broad stakeholder community. IEEE standards set specifications and best practices based on current scientific and technological knowledge. The IEEE-SA has a portfolio of over 1,100 active standards and more than 500 standards under development. For more information visithttp://standards.ieee.org.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence, Mentor Graphics and Synopsys.
