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UMC and Cadence Collaborate to Deliver 28nm Design Reference Flow for ARM Cortex-A7 MPCore-based SoC

SAN JOSE, Calif., 20 Jan 2015

Highlights:

  • Flow included Cadence Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus QRC Extraction Solution, Physical Verification System, Litho Physical Analyzer and CMP Predictor
  • UMC achieves ARM Cortex-A7 performance and power metrics of 1.7GHz and less than 200mW of dynamic power

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a leading global semiconductor foundry, used Cadence® implementation and signoff tools to produce a silicon-ready 28nm ARM® Cortex®-A7 MPCore-based system on chip (SoC) targeting entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. With the Cadence solution, UMC reduced the time to tapeout by 33 percent versus its previous solution and achieved performance of 1.7GHz. In addition, UMC achieved a dynamic power consumption of less than 200mW, which represents a 20 percent reduction over their previous flow.

Using the multi-threaded Encounter® Digital Implementation System, which incorporates GigaOpt route-driven optimization along with CCOpt concurrent clock datapath optimization, resulted in faster turnaround time with significantly improved performance, die area and dynamic power. In addition, the seamless integration of Cadence Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Quantus™ QRC Extraction Solution, Physical Verification System, Litho Physical Analyzer and CMP Predictor allowed UMC to perform signoff checks much earlier in the process to affirm that the design functioned as intended upon completion. 

“The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation and closure so we could quickly deliver a quality reference design to market that exceeded our power, performance and area expectations,” said Shih Chin Lin, senior division director of IP Development and Design Support division at UMC. “Our mobile customers have very specific device requirements, and we’ve tested the new chip to ensure that they have a reliable 28nm silicon-ready reference design.”

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

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