SANTA CLARA, CA – April 14, 2014 – Aprisa™ and ApogeeTM, ATopTech’s place and route solutions, have been certified for the version 1.0 Design Rule Manual (DRM) of TSMC’s 16nm FinFET process . ATopTech, a leader in next generation physical design solutions, continued their ongoing collaboration with TSMC to optimize ATopTech physical implementation tools to support advanced designs in TSMC 16nm FinFET (16FF). The rigorous certification process ensures that ATopTech tools deliver satisfactory quality of results, including design correctness, routability, timing, power, area and manufacturability for designs in 16FF.
Aprisa and Apogee also passed TSMC’s Integrated Tool Certification, where all 16FF design rules and methodologies were validated within the ARM Cortex™ A15 quad-core processor design hardening flow. This certification includes all sign-off checks, including DRC/ LVS (design rule checking/ layout versus schematic), IR/ EM (voltage drop and electro-migration check), MVRC (multi-voltage rule check) and formal verification. Customers can request the Aprisa/Apogee Technology File for 16FF directly from TSMC for immediate 16nm design starts.
The 16FF certification program with Aprisa/Apogee delivers:
- · Design enablement for 16FF DRM v1.0
- · High-R layer optimization
- · Vt min-area pessimism reduction
- · CNOD (continuous OD) cell placement rules enhancement
- · Low-VDD hold time fixing
- · MiM (metal-insulator-metal) capacitor RC extraction and timing impact
- · Standard cell pin access and routability improvement
“We find that many of our joint customers, especially those designing mobile devices, are moving to 16nm to increase the density of transistors and increase operating speed while also reducing power consumption,” said Jue-Hsien Chern, CEO of ATopTech. “Certification into TSMC’s 16FF flow continues to deliver the advanced technology our customers expect from ATopTech.”
“Design teams can be confident that the deep collaboration between ATopTech and TSMC will continue to deliver advanced process technology and accelerated 16nm FinFET development to joint customers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.
About Aprisa
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines,” such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
About Apogee
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floorplanning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
