feature article
Subscribe Now

The Persistence of Memory

Performance-IP’s MRO Speeds up Slow Memories

“If you optimize everything, you will always be unhappy.” — Donald Knuth

Q: When is a cache not a cache?
A: When it’s a Memory Request Optimizer.

If that sounds tautological (aren’t all caches memory-request optimizers?), then you haven’t talked to Performance-IP, a small startup in the Boston area. P-IP has a patent-pending way to speed up your system’s slow accesses to external memory by interposing some clever logic of its own.

The company’s MRO (memory request optimizer) sits between your system bus and your memory controller – like a cache. But it’s not a cache. It monitors requests for external memory reads and supplies data from its own internal storage. But it isn’t a cache. It’s smart about how, when, and where your system is accessing external memory, so it can cut latency by huge amounts, but without being a cache. Its benefits are measurable but also somewhat unpredictable. But it’s still not a cache.

The MRO logic doesn’t have traditional cache tags, so it’s not technically a cache. Instead, it has “trackers,” which serve a similar purpose but in a different manner. You can configure the number of trackers in your implementation of the MRO (it’s supplied as Verilog), so you can tune the number of trackers to balance performance against area and power. As a rule of thumb, you’ll want about 10–20 trackers, although some benchmarks show marked improvement with only four.

The MRO does store data locally, like a cache, and that’s one source of its performance-enhancement capabilities. Its local storage (P-IP calls them response buffers) is undoubtedly faster than your external RAM, so any read “hit” is a performance win.

But its trackers are also proactive, and they will prefetch data based on what they observe about your code’s locality of reference. If its internal statistic-gathering mechanism suggests that you’re accessing a certain range of addresses linearly, it’ll prefetch the upcoming data for you and store it in its response buffer. If all goes according to plan, you’ll be able to skip a couple of external memory reads entirely.

It’s this proactive prefetching that is the other source of MRO’s performance. Unlike a memory scheduler, the MRO doesn’t ever rearrange or reorganize memory accesses. Nothing ever gets delayed, or hoisted up to the front of the queue. Instead, it attempts to apply some rationality to your system’s scattered memory accesses, looking for locality where the compiler couldn’t find any. This is particularly fruitful in multicore and multi-threaded systems where each thread might be perfectly linear, but the combination of all threads/cores together makes for a haphazard melee for memory. MRO tries to stand above the fray, looking for overall patterns that can be exploited for gain.

Naturally, the slower your memory is, the better the MRO works. Or, more accurately, the greater the disparity between your processors’ performance and your memory’s performance, the greater the benefit. Not unlike a cache.

Once you’ve simulated, configured, and installed your MRO, you still have some run-time options available to you. It has three speeds: low, medium, and high (as well as “off”). The distinction is how aggressively the MRO will prefetch data that it thinks you might want. Set the mode too aggressively and you might generate more false fetches than you would see at a lower setting. It’s hard to predict which setting will work best with what software – which is why it’s programmable. Apart from these configuration settings, the MRO is entirely invisible to software. Sort of like a cache.

Performance-IP has lots of benchmark results on its website to show how MRO performs in various modes, with various test suites and various memory speeds. With things configured just right, they’ve seen 88% reductions in memory latency and 50% improvements in CPU performance.

The company doesn’t charge royalties for licensing MRO – just a single up-front licensing fee, with free support. It’s a pretty good deal, if you’ve got the cash.

Leave a Reply

featured blogs
Mar 18, 2024
Innovation in the AI and supercomputing domains is proceeding at a rapid pace, with each new advancement heralding a future more tightly interwoven with the threads of intelligence and computation. Cadence, with the release of its Millennium Platform, co-optimized with NVIDIA...
Mar 18, 2024
Cloud-based EDA tools are critical to accelerating AI chip design and verification; see how NeuReality leveraged cloud-based chip emulation for their 7NR1 NAPU.The post NeuReality Accelerates 7nm AI Chip Tape-Out with Cloud-Based Emulation appeared first on Chip Design....
Mar 5, 2024
Those clever chaps and chapesses at SiTime recently posted a blog: "Decoding Time: Why Leap Years Are Essential for Precision"...

featured video

We are Altera. We are for the innovators.

Sponsored by Intel

Today we embark on an exciting journey as we transition to Altera, an Intel Company. In a world of endless opportunities and challenges, we are here to provide the flexibility needed by our ecosystem of customers and partners to pioneer and accelerate innovation. As we leap into the future, we are committed to providing easy-to-design and deploy leadership programmable solutions to innovators to unlock extraordinary possibilities for everyone on the planet.

To learn more about Altera visit: http://intel.com/altera

featured paper

Reduce 3D IC design complexity with early package assembly verification

Sponsored by Siemens Digital Industries Software

Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D IC design in this new technical paper. As 2.5D and 3D ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process.

Click here to read more

featured chalk talk

Achieving Reliable Wireless IoT
Wireless connectivity is one of the most important aspects of any IoT design. In this episode of Chalk Talk, Amelia Dalton and Brandon Oakes from CEL discuss the best practices for achieving reliable wireless connectivity for IoT. They examine the challenges of IoT wireless connectivity, the factors engineers should keep in mind when choosing a wireless solution, and how you can utilize CEL wireless connectivity technologies in your next design.
Nov 28, 2023
15,199 views