feature article
Subscribe Now

A New Era for EDA?

What’s Next After Moore’s Law

The EDA industry has always been a bit of an enigma. On one hand, EDA has provided the essential technology that has enabled Moore’s Law to proceed for half a century. Without the incredible accomplishments of EDA’s engineers, today’s multi-billion transistor marvels would never have had the chance to exist, and their world-changing capabilities would never have seen the light of day.

Yep, that’s right. I’m saying that without EDA we would not have Pokemon Go. 

At the same time, however, EDA has struggled to claim its just rewards. While the companies in nearly every other part of the ecosystem have started from nothing and become the largest enterprises on Earth, EDA has inched its way over four decades to a paltry total market that would easily be the pocket change left over from a single modern major tech acquisition.

But, could the end of Moore’s Law ironically bring a renaissance for the industry that propelled it to unprecedented heights over the course of the last fifty years? It’s possible that EDA may get some long-needed breathing room, and that just might translate into a much larger audience for companies whose prime user base has been shrinking for a decade or more.

Integration clearly brings incontrovertible benefits. For the entire five decades of Moore’s Law, the top of the food chain has thrived on the ability to maximize single chip integration. Since printing circuits on silicon is essentially free compared with every other way of creating electronic components, the ability to integrate more than the other team has always been a reliable ticket to a market win.

As Moore’s Law has brought exponential growth in our ability to integrate, however, it has also brought exponential growth in the cost of taking advantage of that integration. It is this cost, and the fear surrounding it, that has always attracted EDA marketers. Selling high-priced software tools based on fear of failure was an easy way to make money, and EDA doubled down on that strategy for all it was worth. At the same time, however, EDA utterly failed to make the more direct case for their wares – the productivity advantages it brought to the engineering process. It was just far easier to close a deal when your tools might save engineering management from getting fired for failure than it was to make a case for improved productivity. That kept EDA squarely focused on the pain points of custom chip design on the latest process nodes.

As time passed, however, the number of companies and projects able to take direct advantage of the most advanced semiconductor processes has dwindled. With the cost of producing a custom chip steadily rising, the number of fabs decreasing, and the sophistication of the project pushing hard against the abilities of our very best engineers, more and more projects looked for ways to be competitive without having to create custom chips.

And, luckily, other ways to be competitive has beaten paths to their doors. SoCs are now built in so many variations that it’s hard to come up with a product idea that can’t be built around an inexpensive off-the-shelf SoC. For those that can’t, FPGAs often step in and fill the gap between what can’t be done with an SoC and what can be done with custom hardware. In addition, the ecosystem of ready-made boards and development kits has lowered the barrier to entry on very sophisticated projects.

Throughout all of this, the EDA industry has kept their primary focus on the ever-dwindling audience of custom chip designers. With the demands of each process node causing major tremors that resonated back through the EDA technology base, it took every ounce of engineering that EDA could muster just to deliver a new set of tools every two years that could enable us to design working chips on the latest geometry.

What fell by the wayside through all that chaos was … everything else. EDA remained so focused and dependent on custom IC revenue – from RTL design through layout and verification – that the system, software, FPGA, and PCB realms got only passing attention. Most EDA companies made at least a show of keeping a presence in those businesses, but the industry priority was still to grease the squeaking wheel.

Now, however, we might be rounding the corner to a new era in EDA. As Moore’s Law grinds slowly to a halt, the need to generate ever-more-sophisticated tools to enable the next round of near-atomic dimensions in lithography may slow. That should bring the competitive landscape back from issues like multi-patterning and FinFETS – from the bleeding edge of “can we do any design at all?” to “can we do design efficiently?” Rather than enabling the half-percent of electronic designers who are driving designs on the next node, EDA will need to compete by making the majority of designers more productive.

Of course, EDA has been giving lip service to “system level” design for years. But none of the big three (Synopsys, Mentor, Cadence) has ever generated a significant portion of their revenue on system-level design tools. Mentor and Cadence have always competed vigorously on PCB design as well. But, again, PCB has usually been a stable, low-growth, cash cow – not a critical strategic initiative and not a make-or-break business. Synopsys, the largest EDA company, has basically skipped the PCB market altogether. 

Similarly, EDA companies have shown a passing interest in the software that runs on the SoCs they help to enable. Mentor has been in the embedded software business for two decades, and Cadence followed suit about a decade after. But like system-level design, PCB, and other “diversity” businesses, embedded software has never generated the revenue that keeps the EDA industry alive.

And none of these side businesses in EDA has generated the kind of technological breakthroughs that the industry has produced in custom IC design. It seems, in EDA at least, that necessity truly is the mother of invention. But, that’s not an accident. Invention comes along with talent, and the talent in electronic design automation has always been recruited and applied most aggressively where the business-critical problems lie – in IC design.

EDA has unique intellectual capital – in the hundreds of millions of lines of code that have been developed over the past few decades, in the sophisticated algorithms and methodologies represented by that code base, and most importantly, by a community of talented engineers whose entire careers have been invested in developing and nurturing that technology. That capital could reasonably be reinvested and refocused on propelling electronic technology forward independent of Moore’s Law. EDA could begin a new era by attacking productivity and complexity management at the system level, shortening the development cycle of today’s increasingly complex systems, while at the same time enabling a new generation of systems whose complexity we are just beginning to imagine.

EDA may yet decide to pass on the opportunity, however. The lessons of fear-based sales strategies centered around the edge of Moore’s Law may be hard to un-learn. Engineers whose professional self-esteem has always been rooted in cramming more transistors onto integrated circuits may be reluctant to chase a new goal, and EDA may slowly stagnate as their past breakthroughs are slowly commoditized. It will be interesting to watch.

7 thoughts on “A New Era for EDA?”

  1. Pingback: online casino
  2. Pingback: 6thgear.in
  3. Pingback: must watch
  4. Pingback: DMPK

Leave a Reply

featured blogs
Apr 24, 2024
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Apr 23, 2024
We explore Aerospace and Government (A&G) chip design and explain how Silicon Lifecycle Management (SLM) ensures semiconductor reliability for A&G applications.The post SLM Solutions for Mission-Critical Aerospace and Government Chip Designs appeared first on Chip ...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Addressing the Challenges of Low-Latency, High-Performance Wi-Fi
In this episode of Chalk Talk, Amelia Dalton, Andrew Hart from Infineon, and Andy Ross from Laird Connectivity examine the benefits of Wi-Fi 6 and 6E, why IIoT designs are perfectly suited for Wi-Fi 6 and 6E, and how Wi-Fi 6 and 6E will bring Wi-Fi connectivity to a broad range of new applications.
Nov 17, 2023
20,865 views