Next Up: A Tortoise That Checks Your Chip for Flaws
I hate writing about security. I hate it because I wish it were unnecessary. There was a time when engineering meant making a product that did what you wanted it to do. Now it means spending a bunch of time making it not do what other people want but you don’t want. This sucks.
Most of the problem with implementing security features is guessing where the vulnerabilities are. How do you fix a bug you’ve never even thought of, much less identified? At least “real” hardware bugs are unintentional. Security hacks are both deliberate and malicious. Someone is trying to break your stuff.
Xilinx Announces RFSoCs
CQ CQ CQ - Calling CQ. This is 5G calling...
We’ve all heard it. 5G is coming. Maybe not soon, but as soon as we can get all those pesky technical issues worked out. Which pesky technical issues would those be? Glad you asked. It turns out that cramming a previously unfathomable amount of bandwidth over an unprecedented number of individual connections into each and every cell tower using millimeter wavelengths and 2 dimensional massive multiple-input multiple-output (MIMO) antenna arrays - and doing all of that within acceptable power and footprint constraints - is a really tough problem. Actually, it’s a LOT of really tough problems.
Of Oscillators and IEEE 1588
It’s a quaint tradition, born out of decades of action thrillers summoning teams of protagonists to execute some very precise (and unlikely) plan. As the caper commences, before they disperse, they execute the final ritual: synchronizing watches.
Seems silly these days; quartz and electronics have long ago given us watches that keep excellent time, with no need for constant resetting. What with cell phones doubling as watches, our timing is even better coordinated.
Hoodoo Rituals for New Technology Implementation
This week’s Fish Fry is a virtual bubbling cauldron of hoodoo rituals, VPX goodness, and bat wings. (OK, kidding about the bat wings). First up, I chat with a team from Elma Electronic about the perfect recipe for high speed wizardry in the world of VPX and the rituals we need to perform to get the newest and coolest technology features in OpenVPX. Continuing with our open architecture theme, I chat with Mike Walmsley from TE Connectivity about rugged embedded computing and the trends driving new interconnect design today.
How Hard Can it Be to Count Chips?
One of the questions we often get asked here at EE Journal Galactic Headquarters and Bait Shoppe is, “What is Company X’s market share?” or the corollary question, “How big is the total market for microcontrollers, CPUs, and FPGAs?”
After charging our customary consulting fee, plus tax and 18% gratuity, and after deducting for mileage, food, lodging, client entertainment, and out-of-pocket expenses, our reply is generally, “We don’t know.”
Intel, Microsemi Debut New Families
There is an awful lot of chest beating in the FPGA world. Xilinx and Intel (Altera) have always taken great biennial pride and few prisoners when it comes to building and bragging about the biggest, baddest, fastest, farthest-out slabs of silicon that a few billion dollars worth of semiconductor fab can crank out. Getting to market before the other guy with a high-end Virtex or Stratix family, released on the latest and greatest FinFET-having, low- or high- or we-don’t-care-anymore-K dielectric, tiniest-geometry, most-exotic process has always been the source of utmost pride for the pair of programmable logic provocateurs.
Then, things usually get quiet for awhile.