AMD Fails to Impress

Hierofalcon Processor Does Pretty Much What It’s Supposed To

by Jim Turley

I really wanted to like this chip. But then I talked to the manufacturer.

Let me explain. Your humble servants here at Electronic Engineering Journal talk to a lot of people at a lot of different companies. That’s what we do. The vendors tell us about their whizzy new chip, or new software, or new business venture, or whatever. We listen politely at first, knowing that the vendor will – quite rightly – present the product in its best possible light. That’s their job.

Now, if we were working for some other publications or online journals I could name, we’d just print whatever the vendor told us. “New chip promises to revolutionize Internet of Things!” or “Software update is a game-changer!” or “Company reveals new product and you’ll never guess what happens next!” We’ve all seen those types of breathless (and brainless) headlines. But here at EEJ we like to do a little better. That’s our job.  Read More


Industry News

October 01, 2014

Connect One Launches Next Generation IoT WiFi Modules

Micrium Launches First End-to-End Solution for Internet of Things Device Design

Allegro MicroSystems, LLC Announces New Low-Noise, High-Precision, Factory-Programmed Linear Hall-Effect Sensor IC

Xilinx Showcases All Programmable Solutions for 400GE Applications at WDM Dallas 2014

Produce High Accuracy Analog Output with Ultra-Low Power Consumption

ITTIA Sync Adapter Connects Android to Big Data

Get the Next Bright Idea with the Intel Edison Available from Mouser

Mentor Graphics Embedded Linux Technology Powers Network Functions Virtualization Solution on AMD 64-bit ARM SoC

Synopsys' Galaxy Design Platform Delivers Over 30% Leakage Power Reduction for Fujitsu Semiconductor's ARM-Powered Multi-Core

Altera and ARM Expand Strategic Partnership for SoC Development Tools

ASSET SourcePoint support for 64-bit ARM Embedded Trace Macrocell (ETMv4) on AppliedMicro's X-Gene will speed microserver time-to-market

Express Logic Develops X-Ware Platform™ to Fast-Track ARM-Based IoT Development

Smart energy innovator for developing countries joins IAR Systems’ green technology program

Altium broadens ARM Cortex-M device support to its TASKING C compiler for ARM

September 30, 2014

TSMC and Synopsys Accelerate Custom Design Productivity for 16FF+ Process

Synopsys Announces New Additions to Liberty to Significantly Speed up Timing Closure

IAR Systems dominates the tools market for ARM Cortex-M with leading code efficiency

ATopTech’s Physical Implementation Tools Certified to Support Advanced Designs in TSMC’s 16nm FinFET+ Process

September 29, 2014

Coverity Launches Code Spotter™ in Free Beta Version to Speed Defect Detection in Java Code

Renesas Electronics Expands True Low Power™ RX111 Group Microcontroller Lineup within the 32-Bit RX Family with Larger Memory Capacities up to 512 KB

Cadence IP Portfolio and Tools to Support New TSMC Ultra-Low Power Technology Platform

ARM and Synopsys Expand Collaboration to Improve Quality of Results and Time-to-Results for Leading-Edge ARMv8-A and ARMv7-A Cores

Microsemi Expands Customer Application Design Opportunities by Introducing SmartFusion2 Advanced Development Kit with Largest Density 150K LE Device

Cadence and ARM Expand System-on-Chip Design Collaboration with New Multi-Year Technology Access Agreement

S2C Announces AXI-4 Prototype Ready Quick Start Kit

September 26, 2014

Eurotech Announces Release of Kura 1.0 Java-OSGi Framework for M2M Gateways and Smart Sensor

Versatile Media Isolated Pressure Sensor from Measurement Specialties Withstands Extremely Corrosive Environments

VadaTech Offers Hybrid 2U MicroTCA Chassis Platform with Rear Transition Slots

News Archive

Max 10 Kills the CPLD

Altera Redefines Non-volatile FPGAs

by Kevin Morris

Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

The Beat Goes On

The Cadence of IoT and the Sound of a Single Atom

by Amelia Dalton

The Four Horsemen

What Does the Future Hold for the Semiconductor Industry?

by Dick Selwood

Articles Archive

 

EEJournal On The Scene Video News
 Hosted by Amelia Dalton

editors' blog

Collocated Location Technology

posted by Bryon Moyer

Broadcom brings GNSS and inertial sensors together on a single chip. (Yesterday)

Just What Is the New IEEE Sensor Standard?

posted by Bryon Moyer

IEEE and MIG announced a sensor standard. Depending on what you read, it is about a bunch of different things. Most of which it isn’t really about. Not directly, anyway. (25-Sep)

Turning InGaAs on its Head

posted by Bryon Moyer

Leveraging the cost-effectiveness of silicon for high-performance materials (23-Sep)

M2M in Orbit

posted by Bryon Moyer

Taoglas provides satellite Thing connectivity. (18-Sep)

ProbMe Simplifies Thing WiFi Connection

posted by Bryon Moyer

Some Things are harder to connect to WiFi than your phone or computer. ProbMe tries to make it easier. (16-Sep)

Editors' Blog Archive

 

forum

Expanding EDA

Posted on 10/01/14 at 10:32 AM by bmoyer

bmoyer
Fortunately, I chose a suitably imprecise measure by conjuring up "legions." So I can safely say "yes." smiling

Max 10 Kills the CPLD

Posted on 10/01/14 at 9:28 AM by kevin

kevin
Ouch! Marketing filter... I am shamed. I thought I was a little snarky even, a couple of places. In my defense, the dead CPLD part was completely original. I have always thought it funny that there is a whole class of FPGAs that we still pretend are CPLDs…

Max 10 Kills the CPLD

Posted on 10/01/14 at 3:12 AM by juergenuk

juergenuk
@Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera - Lattice - Microsemi - Xilinx imlementation ( sorry if I forgot some ). I know there are many variants - any example/volume appreciat…

Expanding EDA

Posted on 09/30/14 at 10:10 PM by Kev

Given that the EDA guys are a rather non-"Agile" bunch I'm not sure they're going to get much done.

Personally I think you can re-apply a lot of EDA tools aimed at hardware design at parallel software design. Parallel stuff is hard to debug, so formal …

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:38 AM by SteveCasselman

@juergenuk You can buy a development board with the largest part for $50. The smallest part is 25 times smaller and yet is still large enough to fit a NIOS processor and 16 DSP units plus logic left over.

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:10 AM by juergenuk

juergenuk
I am missing where this new Altera series fits price wise. Lattice never went to the biggest - but instead a market not so much served by A and X. I have been selling against A and X - or more positively, finding the right niches for Lattice.
So Lattice …

Expanding EDA

Posted on 09/29/14 at 9:57 AM by bmoyer

bmoyer
What do you think about the cycles of EDA and EDA's expanding scope?

Who Controls the Power?

Posted on 09/29/14 at 2:11 AM by GuidoGam

Not a single word about Alpha?

There’s a Processor in My FPGA!

Posted on 09/28/14 at 10:35 PM by JohnSwan

JohnSwan
Indeed, Mentor Graphics had the ASAP (Application Specific Assistant Processor)tool 10 years ago. It automated the ability for the user to select a function and push it onto the FPGA fabric. It used an HLS tool of course for the synthesis. Though OpenCL g…

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 Hosted by Amelia Dalton

chalk talks

Hardware/Software Co-Verification of ARM Processor-Based Designs

In this episode of Chalk TalkHD Amelia chats with Lauro Rizzatti of EvE about the latest in emulation technology and explains how you can use emulation to dramatically accelerate software development, which is becoming the most time-consuming part of SoC design.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

IP and Process Solutions for Energy-efficient PMICs

In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.

What is Design Security in a Mainstream SoC?

Do you worry about security in your FPGA design? Are there bad guys out there trying to take advantage of security holes in your electronic designs? What can we do to stop them? In this episode of Chalk Talk, Amelia chats with Tim Morin (Microsemi) about the practical aspects of security in mainstream SoC FPGAs - what threats are out there and what we can all do to help keep the bad guys at bay.

Introducing Digitally Enhanced Power Analog

Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.

Chalk Talk Archive


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